Layout Scale-Up Engineer

About the Mission

Alice & Bob's current 48-qubit generation was hand-drawn - the next generations won't be. As we scale toward 1,000-, 10,000-, and eventually million-qubit chips, manual layout stops being an option: it doesn't scale, and it caps how fast we can iterate. This role exists to build the infrastructure - PDK, generators, automated flows - that lets chip complexity grow 10-1,000× while design cycle time stays flat.

About the Role

You'll build the layout infrastructure that makes that scaling possible - PDK, layout compilers, parasitic extraction, hierarchical verification, and mask generation. This is a semiconductor physical-design role applied to superconducting hardware, not a quantum physics one.

Responsibilities

• Build and own the PDK - layer stack, technology file, parametric cells (junctions, CPW, resonators, couplers, pads, airbridges/crossovers) - and their DRC/LVS decks
• Design a tile-based, hierarchical layout methodology: standardized reticle-compatible tiles, programmatic instantiation, and stitching for wafer-scale and multi-chip designs
• Write and maintain layout generators (Python/GDS or vendor EDA scripting) that turn architecture spec + frequency plan into DRC-clean GDSII/OASIS with zero manual drawing
• Own mask generation end-to-end: floorplan → hierarchical layout → DRC/LVS/PEX signoff → wafer map, test structures, PCM placement → mask data prep and tape-out package
• Drive automation targets: >50% automated layout at 400 qubits, >80% at 1,000, >90% at 10,000+
• Keep DRC/LVS/PEX runtime and file size tractable at 10⁶-10⁸ elements via hierarchical, cell-level, and incremental verification
• Evaluate and deploy the EDA toolchain (Cadence/Siemens/Synopsys-class or open-source) and integrate it with EM-simulation handoff
• Serve as physical-implementation signoff at design review gates ahead of mask release

Requirements

• 5+ years in physical design, custom/analog layout, PDK development, or mask data prep in a semiconductor context (CMOS backend, RF/analog, MEMS, or photonics), including at least one production tape-out owned end-to-end
• Track record scaling a layout methodology - replacing hand-drawn layout with generators, PCells, or hierarchical flows on a design that grew substantially in element count
• Hands-on parasitic extraction experience - commercial (Calibre xRC/xACT, Quantus, StarRC) and/or field-solver-based (FastCap/FastHenry, BEM/FEM) - including deck/rule-file development and correlation against EM or measurement
• Strong layout-automation scripting: Python (gdstk/gdsfactory/KLayout API) and/or vendor languages (SKILL, Tcl)
• Fluent in DRC/LVS deck authoring, GDSII/OASIS, reticle and stepper constraints (field size, stitching, alignment marks), and tape-out data prep
• Comfortable turning a frequency plan or floorplan constraint set into geometry

Nice to Have

• Experience with superconducting or cryogenic device layout (Nb/Ta/TiN/Al thin films, Josephson junctions, CPW resonators, airbridges) and the loss/crosstalk-driven layout rules that come with it

Recruitment Process

• Screening Call with Grace, Talent Acquisition Specialist (30 min)
• Hiring Manager Interview with Felix (45 min)
• Technical Interview/Presentation with the Team (120 min)
• Leadership Team Interview (30 min)
• Fit Interview (45 min)
• Reference check