Analog Layout Design Engineer
Confirmed on the employer's own hiring board on Oct 17, 2026. First seen by Alion on Aug 24, 2026. Altera scores A on the Alion truth index.
Job Details:
Job Description:
We are seeking a skilled and detail-oriented Analog Layout Designer to join our engineering team. In this role, you will be responsible for designing complex layouts of analog signal circuits based on rigorous design specifications. You will execute comprehensive verification flows to ensure top-tier performance, reliability, and manufacturability, while collaborating closely with cross-functional teams to optimize area, power, and yield.
Key Responsibilities
Layout & Floorplanning:
Design complex layouts of analog signal circuits meeting strict design specifications.
Design and analyze floorplans, power grids, ESD protection structures, and bumps for analog blocks.
Perform micro-floorplanning and detailed signal planning for complex analog circuits, ensuring proper shielding and device matching for critical signals.
Verification & Reliability:
Run complete sets of design verification tools to check process design rules (DRC/LVS).
Perform critical reliability checks, including electromigration, voltage drop (IR drop), ESD, and other advanced layout-dependent effects.
Methodology & Innovation:
Develop and drive new, innovative analog layout methodologies to continuously improve layout productivity, efficiency, and quality.
Troubleshoot a wide variety of challenges ranging from design anomalies to tool, flow, and methodology issues.
Cross-Functional Collaboration:
Partner with analog circuit designers, process technology teams, and package design engineers to align on specifications and plan deliverables.
Negotiate layout trade-offs effectively to optimize for area, power, reliability, and overall performance.
Qualifications:
Experience: Proven experience in analog and mixed-signal integrated circuit (IC) layout design.
Technical Expertise:
Strong proficiency in custom layout tools (e.g., Cadence Virtuoso or equivalent).
Deep understanding of physical verification tools (Calibre or equivalent) for DRC, LVS, ANT, and ERC.
Expertise in advanced reliability verifications (EM/IR, ESD, thermal effects).
Solid knowledge of advanced semiconductor process nodes and related layout techniques (matching, shielding, guard rings, common-centroid layout).
Soft Skills: Excellent problem-solving abilities, strong communication skills, and the ability to thrive in a collaborative, cross-functional team environment.