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Salary
≈ $16k – $37k per year (Estimated)
Location
In office (Hyderabad)
Seniority
Junior · 2+ years exp
Employment
Full-Time

Confirmed on the employer's own hiring board on Oct 15, 2026. First seen by Alion on Jul 29, 2026. Altera scores A on the Alion truth index.

Overview
Company
Impact
Profile match
Altera is an American programmable logic company whose field programmable gate array business was founded in 1983, acquired by Intel in 2015 and separated again as a standalone company in 2025 when the private equity firm Silver Lake took a majority stake. It designs FPGAs and structured application specific integrated circuits used where a design must be reconfigurable after manufacture, which makes them common in communications infrastructure, industrial control, automotive, aerospace, defence and test equipment. Headquartered in San Jose, the company sells its Agilex and Cyclone device families alongside the Quartus design software engineers use to program them.

Job Details:

Job Description:

Altera is looking for a talented and drivenDesign Verification Engineer to Designs, develops, validates, and/or debugs software abstractions and frameworks for acceleration with FPGAs to support embedded, data center, and communication clients.

Key Responsibilities:

  • Collaborate with architects and design engineers to understand IP specifications and define comprehensive verification strategies and detailed test plans.

  • Develop robust, reusable, and constrained-random verification environments using SystemVerilog and UVM (Universal Verification Methodology).

  • Create and implement directed and random test cases and test sequences to exercise design functionality and uncover potential bugs.

  • Develop verification components, including drivers, monitors, scoreboards, and checkers.

  • Utilize SystemVerilog Assertions (SVA) and formal verification methods to enhance bug detection and verify complex properties.

  • Execute simulation regressions, debug test failures, analyze root causes, and work with designers to implement corrective measures.

  • Define and track functional and code coverage metrics to ensure verification completeness and drive coverage closure.

  • Develop automation scripts and infrastructure using languages like Python or Perl to improve verification efficiency and flows.

  • Participate in technical reviews of specifications, design documents, and test plans, providing valuable input and feedback.

Qualifications:

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field .

  • 2+ years of experience in ASIC or FPGA design verification.

  • Expertise in Hardware Description Languages (HDL) like Verilog or VHDL and Hardware Verification Languages (HVL) such as SystemVerilog.

  • Strong hands-on experience in developing UVM-based testbenches and verification components.

  • Proficiency in modern verification methodologies, including coverage-driven verification (CDV) and assertion-based verification (ABV).

  • Familiarity with industry-standard protocols such as AMBA (AXI, ACE, CHI, APB), PCIe, or Ethernet is a plus.

  • Experience with simulation and debug tools.

  • Strong scripting skills in Python, Perl, or Tcl for automation and data analysis.

  • Excellent analytical, problem-solving, and debugging skills.

  • Strong communication skills and the ability to work effectively in a collaborative, cross-functional team environment.

Job Type:

Regular

Shift:

Shift 1 (India)

Primary Location:

Regus, Madhapur

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
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