FPGA Development Tools Engineer

Job Details:

Job Description:

We are seeking a senior engineer to join our Device Modeling & Enablement team. In this role, you will develop and automate tests used to validate FPGA device and simulation models used by Altera Quartus Prime. You’ll drive end-to-end validation flows, build and maintain regression infrastructure, analyze results, and collaborate with design teams to ensure high-quality releases across multiple device families. Ideal candidate has:

- a strong foundation in digital design

- hands on experience with FPGA/ASIC development flows

- solid skill in automation and debug

- a strong focus on quality and continuous improvement.

Key Responsibilities

Test Planning and Execution

• Develop comprehensive test plans for device and simulation model validation across Quartus Prime components.
• Execute targeted and regression tests across multiple FPGA device families, configurations, and corner cases.
• Ensure verification coverage aligns with design intent and release quality goals.

Flow and Infrastructure

• Build and run end-to-end Quartus projects to exercise synthesis, fitting, and simulation signoff on representative designs.
• Maintain golden reference results; compare and triage deltas in QoR, performance, resource utilization, and warnings/errors.
• Package and maintain reproducible test kits and reference designs.

Automation, Tooling, and Modeling

• Create and maintain automation and modeling tools using C++, Tcl, Python, and bash for test generation, execution, log mining, and results reporting.

• Develop and maintain C++ device model libraries representing FPGA architecture blocks such as DSP and memory used by synthesis and simulation flows.

• Integrate tests and model validation into CI pipelines (e.g., Jenkins/GitLab CI), including pass/fail gates and artifact tracking.

• Develop utilities to parameterize devices, architectural variants, corners, and random seeds for coverage expansion.

Debug and Quality

• Analyze failures across synthesis, fitter, and device models; isolate root causes across RTL, constraints, tool behavior, and C++ model implementations.

• Collaborate with modeling, device, and software teams to validate fixes and prevent regressions.

• Track and improve key quality metrics (pass rate, coverage, defect density).

Documentation and Process

• Author and maintain test plans, runbooks, and user guides for test environments.
• Contribute to checklists and acceptance criteria for device and model signoff.
• Help improve validation process for better scalability and repeatability.

Qualifications:

Minimum Qualifications

• BS/MS/PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field
• 4-5 year of relevant experience
• Strong foundation in digital design principles: combinational/sequential logic, clocking, resets, pipelining.
• Experience with FPGA or ASIC flows: RTL (Verilog/SystemVerilog or VHDL), synthesis, static timing analysis, and constraints (SDC).
• Proficiency in at least one scripting language (Tcl or Python) and a working foundation in C++ for developing or debugging hardware or device models.
• Familiarity with Linux development environments and build workflows.
• Strong problem-solving skills with the ability to interpret tool logs and timing reports.
• Effective written communication for documentation and clear defect reporting.

Preferred Qualifications

• Experience developing or maintaining C++ libraries for hardware, architectural, or device modeling (e.g., DSP, memory, or timing models).

• Experience with Altera Quartus Prime (Lite/Standard/Pro), including TimeQuest and basic fitter concepts.

• Hands-on experience with version control (Git) and CI systems (Jenkins/GitLab CI).

• Familiarity with device concepts such as speed grades, PVT corners, IO standards, and clocking networks.

• Basic understanding of timing signoff concepts (clocks, generated clocks, I/O delays, false/multicycle paths).

• Coursework or projects involving FPGA boards, EDA tools, or regression test environments.

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