Junior Verification Engineer
Confirmed on the employer's own hiring board on Oct 21, 2026. First seen by Alion on Sep 4, 2026. Altera scores B on the Alion truth index.
Job Details:
Job Description:
We're looking for talented, self-motivated engineers to join our Design Verification (DV) team in a junior or mid-level position. We work on some of the most technically challenging silicon in the industry, spanning digital and analog design, DSP pipelines, and firmware-hardware co-verification.
What We Build
Our team develops and verifies high-speed SerDes IP, the physical layer technology that moves data at speeds from 10Gbps to 100Gbps+ across PCIe, Ethernet, and other industry-standard interfaces. Getting this right matters, the world's data moves through what we build.
What You'll Work On
Constrained-random and coverage-driven verification of complex high-speed SerDes mixed-signal IP, including advanced verification environment development
Validation of DSP datapaths
FW/HW joint verification
Leveraging AI-assisted tools as a core part of your daily engineering workflow
What We're Looking For
Bachelor's degree in EE, CE, or CS - recent graduate with a strong academic record
Solid grasp of digital design, computer architecture, and software programming
Analytical mindset - you enjoy root-causing problems, not just finding them
Ability to thrive in a dynamic, multi-disciplinary environment
Hands-on exposure to SystemVerilog/UVM or Python - a significant advantage, but not required
What We Offer
A collaborative and innovative environment where great ideas come from every level of the team
A great place to work - we take the work seriously, and each other's success personally
Exposure to the full verification lifecycle - from spec to tape-out sign-off
A team culture that embraces modern tooling, including AI-assisted engineering, as a competitive advantage
A real growth path from day one
Qualifications:
Bachelor's degree in electrical engineering, Computer Engineering, or Computer Science
- 0-3 years of industry or academic experience in hardware design or verificationNice to Have
- Hands-on experience with SystemVerilog/UVM
- Python scripting for verification automation
- Familiarity with mixed-signal or analog simulation concepts
- Knowledge of high-speed protocols such as PCIe or Ethernet
- Prior internship or experience in RTL design or verification
- Strong academic record; top graduating students are encouraged to apply