Sr. ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team
Confirmed on the employer's own hiring board on Oct 27, 2026. First seen by Alion on Aug 14, 2025. Amazon scores B on the Alion truth index.
Utility Computing (UC)
AWS Utility Computing (UC) provides product innovations - from foundational services such as Amazon’s Simple Storage Service (S3) and Amazon Elastic Compute Cloud (EC2), to consistently released new product innovations that continue to set AWS’s services and features apart in the industry. As a member of the UC organization, you’ll support the development and management of Compute, Database, Storage, Internet of Things (Iot), Platform, and Productivity Apps services in AWS, including support for customers who require specialized security solutions for customers who require specialized security solutions for their cloud services.
Annapurna Labs (our organization within AWS UC) designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago-even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world.
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Custom SoCs (System on Chip) live at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team you’ll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, our custom designed machine learning inference datacenter server. Our success depends on our world-class server infrastructure; we’re handling massive scale and rapid integration of emergent technologies. We’re looking for an ASIC Design Eengineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right trade-offs.
Key job responsibilities
- integrate multiple subsystems into top level SOC, ensure correct clock/reset/functional/DFT signal routing
- As a key member of the ASIC design team, you will implement and deliver high performance, area and power efficient RTL to achieve design targets and specifications.
- Analyze design, microarchitecture or architecture to make trade-offs based on features, power, performance or area requirements.
- Develop micro-architecture, implement SystemVerilog RTL, and deliver synthesis/timing clean design with constraints.
- Perform lint and clock domain crossing quality checks on the design.
- Work with with architects, other designers, verification teams, pre- and post-silicon validation teams, synthesis, timing and back-end teams to accomplish your tasks.
You will thrive in this role if you:
- Are familiar with scripting in Python
- Are proficient with assertions
- Have good debug skills to analyze RTL test failures
- Have a "Learn and Be Curious" mindset
About the team
Custom SoCs (System on Chip) live at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team you’ll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, our custom designed machine learning inference datacenter server. Our success depends on our world-class server infrastructure; we’re handling massive scale and rapid integration of emergent technologies. We’re looking for an ASIC Design Eengineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right trade-offs.
Our team is dedicated to supporting new members. We have a broad mix of experience levels and tenures, and we’re building an environment that celebrates knowledge-sharing and mentorship. Our senior members enjoy one-on-one mentoring and thorough, but kind, code reviews. We care about your career growth and strive to assign projects that help our team members develop your engineering expertise so you feel empowered to take on more complex tasks in the future.
Basic qualifications
- B.S. in Electrical Engineering or related technical field
- 5+ years in RTL design for SOC
- 5+ years of VLSI engineering
- 5+ years with code quality tools including: Spyglass, LINT, or CDC
Preferred qualifications
- Master's degree in electrical engineering, computer engineering, or equivalent
- Experience with Microarchitecture, SystemVerilog RTL, Assertions, SDC constraints
- Experience with automation and scripting languages such as Python
- Familiarity with data path design, interconnects, AXI protocol
- Good analytical, problem solving, and communication skills
Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status.
Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner.
The base salary range for this position is listed below. Your Amazon package will include sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave. Learn more about our benefits at https://amazon.jobs/en/benefits.
USA, TX, Austin - 185,200.00 - 250,000.00 USD annually