ASIC Design STA Engineer
Confirmed on the employer's own hiring board on Oct 24, 2026. First seen by Alion on Apr 17, 2026. AMD scores B on the Alion truth index.
WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gamingand embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuityand a shared passion to create something extraordinary. When you join AMD, you’lldiscover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.Together, we advance your career.
THE ROLE:
AMD is looking for an ASIC Design STA engineer to contribute to the development of large SoCs, featuring multiple physical blocks and over 300 clock domains. The candidate's responsibilities will include building and verifying timing constraints for intricate SoC designs. This role demands a combination of SDC expertise, EDA tool proficiency, and TCL-based scripting abilities. The candidate should possess extensive experience in SDC development and debugging, be familiar with enhancing various RTL quality metrics for complex, hierarchical designs, and be able to automate these processes for increased efficiency. Proficiency in both front-end (RTL) processes and back-end (Synthesis and P&R) processes is preferred.
THE PERSON:
High energy candidates with strong written and verbal communication skills, and structured, well-organized work habits will be successful. Team and goal oriented are essential.
KEY RESPONSIBILITIES:
- Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff
- Lead the effort to maintain RTL quality metrics in complex, hierarchical designs, while automating the process for increased efficiency.
- Implement the pre-route timing checks and QoR clean up to eliminate timing constraints issues and ensure a quality handoff for STA checks.
- collaborate with CAD on the development of pre-production synthesis (Design Compiler) and STA (Primetime) work flows.
- Require a blend of SDC expertise, proficiency in EDA tools, and Tcl based scripting abilities (in both EDA environment and standalone Linux Tcl shell scripts)
PREFERRED EXPERIENCE:
- Worked with EDA tools that enable RTL quality checks
- Hands on experience in building the timing constraints for IPs, blocks and Full-chip implementation in both flat/hierarchical flows.
- Experience with analyzing the timing reports and identifying both the design and constraints related issues.
- Ability to multitask, grasp new flows/tools/ideas.
- Experience in improving the methodologies.
- Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail etc.
- Prior experience developing complex TCL scripts in Synopsys Design Compiler (DC) and PrimeTime (PT)
- Writing custom TCL QC and QoR checks using DC/PT object attributes queries and filters
- Strong analytical and problem-solving skills
ACADEMIC CREDENTIALS:
- Bachelors or Masters degree in computer engineering/Electrical Engineering or a related field
LOCATION: San Jose, CA
This role is not eligible for visa sponsorship.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
THE ROLE:
AMD is looking for an ASIC Design STA engineer to contribute to the development of large SoCs, featuring multiple physical blocks and over 300 clock domains. The candidate's responsibilities will include building and verifying timing constraints for intricate SoC designs. This role demands a combination of SDC expertise, EDA tool proficiency, and TCL-based scripting abilities. The candidate should possess extensive experience in SDC development and debugging, be familiar with enhancing various RTL quality metrics for complex, hierarchical designs, and be able to automate these processes for increased efficiency. Proficiency in both front-end (RTL) processes and back-end (Synthesis and P&R) processes is preferred.
THE PERSON:
High energy candidates with strong written and verbal communication skills, and structured, well-organized work habits will be successful. Team and goal oriented are essential.
KEY RESPONSIBILITIES:
- Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff
- Lead the effort to maintain RTL quality metrics in complex, hierarchical designs, while automating the process for increased efficiency.
- Implement the pre-route timing checks and QoR clean up to eliminate timing constraints issues and ensure a quality handoff for STA checks.
- collaborate with CAD on the development of pre-production synthesis (Design Compiler) and STA (Primetime) work flows.
- Require a blend of SDC expertise, proficiency in EDA tools, and Tcl based scripting abilities (in both EDA environment and standalone Linux Tcl shell scripts)
PREFERRED EXPERIENCE:
- Worked with EDA tools that enable RTL quality checks
- Hands on experience in building the timing constraints for IPs, blocks and Full-chip implementation in both flat/hierarchical flows.
- Experience with analyzing the timing reports and identifying both the design and constraints related issues.
- Ability to multitask, grasp new flows/tools/ideas.
- Experience in improving the methodologies.
- Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail etc.
- Prior experience developing complex TCL scripts in Synopsys Design Compiler (DC) and PrimeTime (PT)
- Writing custom TCL QC and QoR checks using DC/PT object attributes queries and filters
- Strong analytical and problem-solving skills
ACADEMIC CREDENTIALS:
- Bachelors or Masters degree in computer engineering/Electrical Engineering or a related field
LOCATION: San Jose, CA
This role is not eligible for visa sponsorship.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.