Silicon Design Engineer

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THE ROLE:

As a member of the Fullchip Floorplan CAD team, you will help develop and enable advanced full-chip physical design methodologies for cutting-edge SoC designs. You will focus on Fullchip Floorplan flow development, working closely with project teams to deliver robust and scalable solutions for complex full-chip designs.

As a senior technical contributor, you will own key methodologies from concept through production deployment, drive technical direction, resolve complex design and flow challenges, and provide technical leadership across multiple engineering teams.

THE PERSON:

The successful candidate will be a highly motivated and experienced silicon design engineer with a strong background in physical design and CAD methodology development. The candidate should be able to independently drive complex technical problems, define solutions, and collaborate effectively across organizational and geographical boundaries.

The candidate will demonstrate strong technical leadership, ownership, communication, and problem-solving skills, with the ability to mentor engineers, influence technical decisions, and drive methodology improvements from initial development through successful production adoption.

KEY RESPONSIBILITIES:

• Own and drive major functions' methodology and flow development for large-scale SoC designs.
• Develop methodologies to identify and optimize repeater and feedthrough requirements based on floorplan, connectivity, timing, hierarchy, and physical constraints.
• Drive complex technical issues to resolution across timing, long-distance interconnect, hierarchy, placement, congestion, and routability.
• Develop robust and scalable CAD automation using Tcl, Python, Perl.
• Drive methodology and flow improvements from concept, prototyping and validation through production deployment.
• Work across Physical Design, Front-End Design/Integration, Timing teams to align requirements and ensure successful methodology integration.
• Provide technical leadership and guidance, conduct technical reviews, and mentor junior engineers.
• Proactively identify methodology gaps, propose solutions, and drive continuous improvements in quality, scalability, runtime, robustness, and usability.
• Support production projects, analyze complex flow issues, drive root-cause analysis, and develop systematic solutions to prevent recurrence.
• Communicate technical strategy, implementation status, risks, and recommendations clearly to engineering stakeholders and leadership.

PREFERRED EXPERIENCE:

• Strong understanding of ASIC physical design fundamentals, including floorplanning, placement, routing, timing analysis, hierarchical design, and timing closure.
• Experience with full-chip physical design, particularly long-distance interconnect optimization, repeater/buffer insertion, feedthrough planning, or related methodologies.
• Experience with physical design tools such as Cadence Innovus and/or Synopsys Fusion Compiler/ICC2.
• Strong programming and scripting skills in Tcl, Python, Perl.
• Demonstrated experience developing and deploying CAD/EDA methodologies and automation for large-scale SoC designs.
• Proven ability to independently drive complex methodology development from problem definition and solution architecture through implementation, validation, and production deployment.
• Experience providing technical leadership, mentoring engineers, and driving cross-functional technical decisions.
• Excellent debugging and analytical skills with the ability to identify root causes and develop scalable solutions rather than testcase-specific fixes.
• Strong communication skills and demonstrated ability to collaborate with multiple engineering teams.

ACADEMIC CREDENTIALS:

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

• #LI-JW3

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

THE ROLE:

As a member of the Fullchip Floorplan CAD team, you will help develop and enable advanced full-chip physical design methodologies for cutting-edge SoC designs. You will focus on Fullchip Floorplan flow development, working closely with project teams to deliver robust and scalable solutions for complex full-chip designs.

As a senior technical contributor, you will own key methodologies from concept through production deployment, drive technical direction, resolve complex design and flow challenges, and provide technical leadership across multiple engineering teams.

THE PERSON:

The successful candidate will be a highly motivated and experienced silicon design engineer with a strong background in physical design and CAD methodology development. The candidate should be able to independently drive complex technical problems, define solutions, and collaborate effectively across organizational and geographical boundaries.

The candidate will demonstrate strong technical leadership, ownership, communication, and problem-solving skills, with the ability to mentor engineers, influence technical decisions, and drive methodology improvements from initial development through successful production adoption.

KEY RESPONSIBILITIES:

• Own and drive major functions' methodology and flow development for large-scale SoC designs.
• Develop methodologies to identify and optimize repeater and feedthrough requirements based on floorplan, connectivity, timing, hierarchy, and physical constraints.
• Drive complex technical issues to resolution across timing, long-distance interconnect, hierarchy, placement, congestion, and routability.
• Develop robust and scalable CAD automation using Tcl, Python, Perl.
• Drive methodology and flow improvements from concept, prototyping and validation through production deployment.
• Work across Physical Design, Front-End Design/Integration, Timing teams to align requirements and ensure successful methodology integration.
• Provide technical leadership and guidance, conduct technical reviews, and mentor junior engineers.
• Proactively identify methodology gaps, propose solutions, and drive continuous improvements in quality, scalability, runtime, robustness, and usability.
• Support production projects, analyze complex flow issues, drive root-cause analysis, and develop systematic solutions to prevent recurrence.
• Communicate technical strategy, implementation status, risks, and recommendations clearly to engineering stakeholders and leadership.

PREFERRED EXPERIENCE:

• Strong understanding of ASIC physical design fundamentals, including floorplanning, placement, routing, timing analysis, hierarchical design, and timing closure.
• Experience with full-chip physical design, particularly long-distance interconnect optimization, repeater/buffer insertion, feedthrough planning, or related methodologies.
• Experience with physical design tools such as Cadence Innovus and/or Synopsys Fusion Compiler/ICC2.
• Strong programming and scripting skills in Tcl, Python, Perl.
• Demonstrated experience developing and deploying CAD/EDA methodologies and automation for large-scale SoC designs.
• Proven ability to independently drive complex methodology development from problem definition and solution architecture through implementation, validation, and production deployment.
• Experience providing technical leadership, mentoring engineers, and driving cross-functional technical decisions.
• Excellent debugging and analytical skills with the ability to identify root causes and develop scalable solutions rather than testcase-specific fixes.
• Strong communication skills and demonstrated ability to collaborate with multiple engineering teams.

ACADEMIC CREDENTIALS:

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

• #LI-JW3

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.