Staff Package Design Engineer
Confirmed on the employer's own hiring board on Oct 21, 2026. First seen by Alion on Oct 19, 2026.
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THE ROLE:
We are looking for a Senior or Staff Package Design Engineer to own the design of advanced IC packages from concept through tape-out and production. You will work with SoC, silicon, signal integrity, power integrity, thermal, and manufacturing teams. Your goal is to make sure our packages meet electrical, mechanical, thermal, and cost targets for high-speed interfaces such as LPDDR5X/LPDDR6, PCIe, and die-to-die links. You will also set design methodology and mentor other engineers. We have competitive benefit packages and an award-winning culture. Join us!
THE PERSON:
As a Staff Package Design Engineer, you will be responsible for the electrical, physical, and mechanical design of advanced semiconductor packages, ensuring optimal signal integrity, power integrity, and manufacturability. You will collaborate closely with cross-functional teams in silicon design, system architecture, signal/power integrity, substrate vendors, and assembly/test operations to deliver high-performance, cost-effective, and reliable package solutions for next-generation products.
KEY RESPONSIBILITIES:
- Execute package substrate design from concept through production release, including floorplanning, routing, stack-up definition, and design rule validation.
- Partner with AMD architects, designers, and product owners to define high yielding, cost effective substrate solutions which meet product requirements
- Define and implement package architecture based on product electrical, thermal, and mechanical requirements.
- Work with chip, board, and system teams to optimize I/O planning, bump/ball assignments, and interface signal integrity.
- Conduct design feasibility studies and trade-off analysis for performance, cost, and reliability.
- Drive DFX (Design for Manufacturability, Assembly, and Test) into the package design process.
- Perform modelling extraction for signal integrity and power integrity analysis, including high-speed interfaces (DDR/LPDDR, PCIe, SerDes, die-to-die links) and PDN impedance. Close design issues through layout changes and stack-up tuning.
- Collaborate with signal integrity (SI), power integrity (PI), and thermal analysis teams to ensure robust performance across operating conditions.
- Interface with substrate suppliers to define design rules, stack-ups, and material selection.
- Contribute to design automation and flow improvement, scripting, and methodology development for package design efficiency.
PREFERRED EXPERIENCE:
- 5-10 years of relevant experience in IC or package design, preferably in advanced flip-chip, SiP, PoP, or 2.5D/3D packaging.
- Experience with high-speed interfaces (LPDDR, PCIe, SerDes, HBM, etc.).
- Strong understanding of substrate design flows (Cadence APD/SIP, Allegro).
- Experience in bump/ball map planning, layer stack-up, and design rule management.
- Familiarity with manufacturing constraints and materials (BT, ABF, coreless, etc.).
- Excellent problem-solving, communication, and cross-functional collaboration skills.
- Solid knowledge of signal integrity, power integrity fundamentals, and thermal considerations in package design is a plus.
- Experience with analysis tools such as Ansys HFSS/SIwave/Q3D, Cadence Sigrity, or Keysight ADS is a plus.
- Basic scripting ability (SKILL, etc.) for design automation is a plus.
ACADEMIC CREDENTIALS:
- Bachelor’s or Master’s degree in Electrical Engineering, Mechanical Engineering, Materials Science, or related field.
LOCATION:
Penang, Malaysia
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
THE ROLE:
We are looking for a Senior or Staff Package Design Engineer to own the design of advanced IC packages from concept through tape-out and production. You will work with SoC, silicon, signal integrity, power integrity, thermal, and manufacturing teams. Your goal is to make sure our packages meet electrical, mechanical, thermal, and cost targets for high-speed interfaces such as LPDDR5X/LPDDR6, PCIe, and die-to-die links. You will also set design methodology and mentor other engineers. We have competitive benefit packages and an award-winning culture. Join us!
THE PERSON:
As a Staff Package Design Engineer, you will be responsible for the electrical, physical, and mechanical design of advanced semiconductor packages, ensuring optimal signal integrity, power integrity, and manufacturability. You will collaborate closely with cross-functional teams in silicon design, system architecture, signal/power integrity, substrate vendors, and assembly/test operations to deliver high-performance, cost-effective, and reliable package solutions for next-generation products.
KEY RESPONSIBILITIES:
- Execute package substrate design from concept through production release, including floorplanning, routing, stack-up definition, and design rule validation.
- Partner with AMD architects, designers, and product owners to define high yielding, cost effective substrate solutions which meet product requirements
- Define and implement package architecture based on product electrical, thermal, and mechanical requirements.
- Work with chip, board, and system teams to optimize I/O planning, bump/ball assignments, and interface signal integrity.
- Conduct design feasibility studies and trade-off analysis for performance, cost, and reliability.
- Drive DFX (Design for Manufacturability, Assembly, and Test) into the package design process.
- Perform modelling extraction for signal integrity and power integrity analysis, including high-speed interfaces (DDR/LPDDR, PCIe, SerDes, die-to-die links) and PDN impedance. Close design issues through layout changes and stack-up tuning.
- Collaborate with signal integrity (SI), power integrity (PI), and thermal analysis teams to ensure robust performance across operating conditions.
- Interface with substrate suppliers to define design rules, stack-ups, and material selection.
- Contribute to design automation and flow improvement, scripting, and methodology development for package design efficiency.
PREFERRED EXPERIENCE:
- 5-10 years of relevant experience in IC or package design, preferably in advanced flip-chip, SiP, PoP, or 2.5D/3D packaging.
- Experience with high-speed interfaces (LPDDR, PCIe, SerDes, HBM, etc.).
- Strong understanding of substrate design flows (Cadence APD/SIP, Allegro).
- Experience in bump/ball map planning, layer stack-up, and design rule management.
- Familiarity with manufacturing constraints and materials (BT, ABF, coreless, etc.).
- Excellent problem-solving, communication, and cross-functional collaboration skills.
- Solid knowledge of signal integrity, power integrity fundamentals, and thermal considerations in package design is a plus.
- Experience with analysis tools such as Ansys HFSS/SIwave/Q3D, Cadence Sigrity, or Keysight ADS is a plus.
- Basic scripting ability (SKILL, etc.) for design automation is a plus.
ACADEMIC CREDENTIALS:
- Bachelor’s or Master’s degree in Electrical Engineering, Mechanical Engineering, Materials Science, or related field.
LOCATION:
Penang, Malaysia
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.