First seen by Alion on Oct 9, 2026.
Job Responsibilities
- Work with the front-end design team to completethe chip floorplan, clock architecture, and powerplan.
- Responsible for backend/PD tasks from theNetlist to the GDSII, including P&R, formal verification, static timinganalysis, physical verification, power analysis, design for reliability andtape-out.
- Research the physical design methodology ofadvanced process nodes, and builds an automatic physical design platform.
Qualifications
- Bachelor's degree or above in electronic engineering, microelectronics, or computer science.
- At least five (5) years of work experience in Place & Route. Hands-on project experience at advanced technology is required.
- Strong communication ability, good confidence and self-motivation.
Skills
Physical Verification, Written and Verbal Communication Abilities, Static Timing Analysis, Microelectronics, Process Engineering Design, Computer Science, Formal Verification, Self-confidence, Routes to Market, Electronic and Electrical Engineering, P&L, Senior Services, design for reliability, Power Calculation, Liaising With Design Team, technical verification

