IC Package / PCB Layout Engineer (d/m/f)

• Design and develop RF and high-frequency IC substrate and PCB layouts for sensor, and mixed-signal applications, ensuring compliance with electrical, thermal, and manufacturing requirements
• Perform RF-aware component placement and transmission line routing, including controlled impedance structures, differential pairs, coplanar waveguides (CPW), microstrip, and stripline implementations
• Optimize layout for signal integrity (SI), power integrity (PI), and RF performance, minimizing coupling, crosstalk, insertion loss, return loss, and electromagnetic interference (EMI)
• Create and maintain package substrate and PCB layouts using Cadence Allegro Suite (Allegro X, APD), Altium Designer and/or Siemens PADS including design libraries, stack-ups, and constraint management
• Collaborate with EMC, analog, package, and IC design engineers to support chip-package-board co-design and ensure successful integration of high-frequency circuits and support for simulation activities using SI/PI/EM extraction tools
• Perform design verification and manufacturability reviews, including DRC/ERC checks, fabrication rule compliance
• Supplier selection and qualification for PCB and SMT (surface mount technology), including supply chain and assembly support

Who we are looking for

• Bachelor's or Master's Degree in Electrical Engineering, Microelectronics, Semiconductor Physics, Computer Engineering, or a related field
• Minimum of 6 years experience in Semiconductor/Electronic Industry
• Strong experience with Cadence Allegro Suite (Allegro X, APD, Package Designer) and/or Altium Designer
• Experience with Cadence Virtuoso Suite and Physical Verification Tools such as Siemens Calibre/Candence PVS of is highly desirable
• Knowledge of semiconductor processes, analog/mixed-signal design considerations, and ESD/EMC concepts is considered a strong benefit
• Knowledge of controlled impedance routing, electromagnetic coupling, grounding strategies, shielding concepts, and RF matching networks
• Experience with IC package substrates, HDI PCB technologies, BGA, wirebond, and flip-chip packaging
• CMOS IC layout experience is highly desirable, providing valuable expertise in parasitic control, matching techniques, device placement, shielding concepts, and chip-package-board co-design
• Good technical English is a must, German is beneficial

We offer competitive salaries and additional benefits based on your performance, experience and qualification.

The employment is in accordance with the collective salary and wage agreement for employees of the electrical and electronics industry, employment group G (https://www.feei.at/aktuelles/mindestloehne-und-gehaelter-eei/).

We offer a higher compensation depending on your expertise and skills.

Please contact Hana Krsul for further information via [email protected] or +43 664 9665611.