Senior Design Verification Engineer

We are seeking a highly motivated and experienced Senior Staff Design Verification Engineer to drive and collaborate on verification activities for complex semiconductor products. This is a senior individual contributor role focused on delivering high-quality verification solutions for advanced digital and mixed-signal integrated circuits.

The ideal candidate will be an expert in SystemVerilog and UVM-based verification methodologies, capable of independently driving verification planning, execution, coverage closure, and debug activities from specification through tapeout. The role offers the opportunity to grow into technical leadership through influence, expertise, and ownership of critical verification deliverables.

Key Responsibilities: Verification Planning and Execution

• Develop comprehensive Design Verification (DV) plans and verification strategies; define verification scope, coverage goals and signoff criteria
• Identify and mitigate functional verification risks

Verification Environment Development

• Architect, implement, and maintain reusable UVM-based environments
• Develop assertions, scoreboards, checkers, and coverage models

Design Verification

• Perform block-level, subsystem-level, and full-chip verification
• Analyze architecture specifications and derive verification requirements
• Debug complex RTL, testbench, and integration issues

Cross-Functional Collaboration

• Work closely with Design, Architecture, AMS, Firmware, and Validation teams
• Participate in design reviews and verification reviews; support customer technical discussions
• Communicate verification status, risks, and closure metrics

Who we are looking for

Education and Experience

• Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field with 8+ years of relevant industry experience (preferred)
• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field with 10+ years of relevant industry experience (minimum qualification)

Required Technical Skills

• Expert-level proficiency in SystemVerilog and UVM
• Strong knowledge of functional coverage development and coverage-driven verification
• Strong debug and root-cause analysis skills
• Creation of scoreboards, monitors, agents, predictors, and coverage models
• Block-level, subsystem-level, and full-chip verification experience
• Verification planning and execution from specification through signoff
• Strong understanding of digital design fundamentals and ASIC/SoC architectures
• Experience reviewing RTL and identifying verification risks
• Familiarity with scripting languages such as Python, Perl, or Tcl

Why Join Us

You will contribute to the verification of next-generation sensor and semiconductor products while working with a highly experienced engineering team. This role offers significant technical ownership, opportunities to shape verification methodology, and a path toward future technical leadership within the organization.

Please contact Joanely Ivette Mortimer for further information via [email protected]