ASIC Design Engineer - Cache Controller
Confirmed on the employer's own hiring board on Nov 14, 2026. First seen by Alion on Jul 29, 2026. Apple scores A on the Alion truth index.
Apple is building the world’s fastest highly parallel mobile processing systems. Our high-bandwidth multi-client memory subsystems are blazing new territory with every generation. As we increase levels of parallelism, bandwidth and capacity, we are presented with design challenges exacerbated by clients with varying but simultaneous needs such as real-time, low latency, and high-bandwidth. In this role, you will work on crafting special purpose cache and controller which is part and parcel of the SOC memory hierarchy.
Description
Design and develop hardware for cache subsystem in high performance system on a chip (SoC).
Develop cache micro-architecture based on architecture guidelines and model analysis.
Explore architecture trade-offs in system performance, area, and power consumption.
Develop and debug register-transfer level (RTL) design of various sections in the cache subsystem.
Work on front-end netlist and area/timing analysis of the cache subsystem.
Work with physical design team on the timing closure of the cache subsystem.
Minimum Qualifications
In-depth knowledge of memory subsystem
Academic experience with RTL/micro-architecture development
Good understanding of PPA (performance/power/area) tradeoffs
B.S. in a relevant field + 0 years of industry experience
Preferred Qualifications
Cache design background including good understanding of different memory organizations and tradeoffs
Experience with multi-processor cache coherence protocols
Knowledge of high-performance coherent memory systems or interconnect architectures
Knowledge of high-performance DRAM controller
M.S in a relevant field.