ASIC Design Engineer — Neural Engine DMA

Computational photography, live language translation, and countless other on-device AI

capabilities depend on moving enormous amounts of data between memory and compute at

exactly the right time. As part of our Silicon Engineering Group, you will design the

high-performance DMA engines responsible for moving model weights and activation tensors

between the memory subsystem and the Apple Neural Engine.

In this role, you will take end-to-end ownership of complex DMA subsystem blocks, shape

technical direction across the team, and mentor engineers earlier in their careers. The

work you drive ships in Apple products used by billions of people every day.

Description

As an ASIC Design Engineer on the ANE DMA Design team, you will drive the design

of DMA subsystem blocks from microarchitecture specification through tapeout. ANE DMA's

scale and complexity means grappling with:

decomposing tensor surfaces into efficient fetch sequences; maximizing throughput under

real-world memory system conditions; maintaining data consistency across concurrent

streams; multi-level arbitration and ordering correctness; sizing latency-tolerant

buffering structures; and security and state isolation.

In this front-end design role, your work will include:

- Taking end-to-end ownership of DMA subsystems through the full cycle: microarchitecture

specification, RTL implementation, front-end signoff (synthesis, timing closure, area

and power analysis, linting, LEC), and design verification closure.

- Writing well-parameterized RTL structured for clean timing and low power, including

assertions and cover points that encode design intent and ensure verification

completeness.

- Collaborating across design, architecture, and physical implementation teams to make

sound architectural trade-offs and drive solutions that meet performance, power, and

area targets.

- Working closely with design verification and formal verification teams to ensure

functional correctness: reviewing test plans, debugging failures, and confirming the

design's intended behavior is fully exercised.

Minimum Qualifications

Bachelors Degree plus 10 years of industry experience

Preferred Qualifications

Experience designing SoC front-end RTL in Verilog or SystemVerilog through multiple

tapeouts, including synthesis, timing closure, area and power analysis, linting, and

logic equivalence checks.

Experience collaborating across design verification, formal verification, architecture,

and physical implementation teams to specify, implement, and debug complex RTL blocks.

Experience designing DMA microarchitecture: address sequencing, flow control,

arbitration, or transaction ordering.

Experience with on-chip bus protocols (AMBA AXI, AHB, APB) and on-chip interconnect

fabrics.

Background in adjacent high-bandwidth domains: networking SoCs, image and video

processing pipelines, multimedia IP, or AI/ML accelerators.

A track record of writing precise, thorough micro-architectural specifications that

serve as the authoritative reference for design, verification, and integration teams.

Familiarity with scripting languages (Python, Perl, Tcl) for design automation.