CAD Engineer – Design Verification Methodology
Confirmed on the employer's own hiring board on Nov 11, 2026. First seen by Alion on Apr 15, 2026. Apple scores A on the Alion truth index.
Do you love building elegant solutions to highly complex challenges? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices!
Description
As a member of our CAD team, you will develop, maintain, and enhance existing sophisticated software systems for regression-testing Apple’s silicon designs in software simulation, to find and report defects in our chip designs, and thus ensure that Apple tapes-out world-class silicon. Your experience and innovative ideas will inform the design of the next generation of these regression systems. Your experience and insight, your skill at diagnosing the root cause of complex problems, and your ability to guide engineers who come to you with problems will be important contributions to an extended CAD team that comprehensively supports Apple’s DV and chip design engineering efforts. You will work closely with EDA vendors to incorporate new capabilities of their commercial tools, and to resolve problems.
Minimum Qualifications
Minimum of BS degree + 10 years of relevant experience
Experience developing, maintaining, and enhancing an existing system for regressing RTL
Experience debugging vendor tool problems
Python programming background is required
Preferred Qualifications
Experience with TCL or Perl is a plus
Experience with artificial intelligence and machine learning
Experience with interacting with DV team(s) to help solve their problems.
Experience in implementing new functionality to solve emerging problems or to optimize already existing methods.
MSEE/CE/CS preferred.
Knowledge in Verilog and SystemVerilog; familiarity with VHDL a plus.
Experience with VCS, XCelium, or Modelsim simulation tools.
Experience with Cadence or Synopsys Emulation tools.
Good communications skills are required and prior customer support experience is a plus.
Familiarity with Verdi and/or Indago is considered a plus.
Knowledge of C and C++ is a plus.