Gate-level SigEM/SEB/FIT CAD Engineer
Confirmed on the employer's own hiring board on Oct 27, 2026. First seen by Alion on Oct 15, 2026. Apple scores A on the Alion truth index.
Imagine what you could do here! At Apple, new ideas have a way of becoming phenomenal products very quickly. Do you want to bring passion and dedication to your job? There's no telling what you could accomplish at Apple. The people who work here have reinvented entire industries with Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices - we continue to strengthen our commitment to leave the world better than we found it!
As an emerging member of our best-in-class CAD Group, you will be part of building innovative designs. You will leverage your strong engineering fundamentals in electrical engineering and computer science-paired with an eagerness to learn electromigration (EM), Statistical Electromigration Budgeting (SEB), Failure In Time (FIT), Self-Heating Effect (SHE), and thermal analysis-to assist in developing, maintaining, and refining methodologies and flows for gate-level as well as transistor-level designs. You will support tasks spanning IP / SOC signal EM analysis for clock and data nets, SOC FIT budget verification, power-grid EM checks, and flow automation. Are you ready to join some of the world's leading engineers, and help us deliver the next generation of ground-breaking Apple products?
Description
In this visible role, your primary responsibilities will include:
- Assist senior engineers in the development, testing, and deployment of EM/SEB/thermal analysis methodologies and flows
- Support the automation, maintenance, and regression testing of CAD flows from setup through sign-off
- Help run, validate, and debug simulation and verification runs on benchmark and production designs
- Assist in developing and maintaining verification scripts and rule checks for clock trees, high-speed data paths, and critical signal nets
- Partner with senior team members to support cross-functional teams (Physical Design, Timing, Circuit Design, Power) by triaging flow execution issues and gathering data
Minimum Qualifications
BS or MS degree in Electrical Engineering or a related field
Preferred Qualifications
Strong academic foundation in VLSI design, semiconductor physics, circuit theory, or computer engineering
Basic understanding of electromigration (EM) mechanisms, heating effects, current density, or chip reliability concepts
Exposure to fundamental concepts in static timing analysis (STA), circuit simulation (SPICE), parasitic extraction, or physical design principles
Proficiency in at least one of Tcl, Python, or Perl scripting languages
High motivation, strong problem-solving abilities, and eagerness to learn complex CAD methodologies
Prior internship, co-op, or academic research experience in VLSI design, CAD/EDA flow development, or chip reliability
Familiarity or hands-on exposure to commercial EDA tools (e.g., Voltus, RedHawk, Primetime, ICC2, Innovus, or SPICE simulators) through coursework or projects is a plus
Curiosity about or coursework in AI/ML applications in CAD/EDA workflows
Proactive attitude with a demonstrated ability to learn quickly under mentorship and guidance
Strong collaboration and communication skills