GPU Physical Design Clocking Engineer
Confirmed on the employer's own hiring board on Nov 11, 2026. First seen by Alion on Feb 13, 2026. Apple scores A on the Alion truth index.
Do you love building elegant solutions to highly complex challenges? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC)! You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, we will enable our customers to do all the things they love with their devices. This role requires a mix of strategic engineering along with hands-on, technical work. You will be implementing complete chip design from netlist to tapeout. You will have hands on experience in physical design and large chip integration.
Description
As a GPU Clocking engineer, you will collaborate with FE teams to understand chip architecture and drive clocking aspects early in design cycle. You will drive best in class clocking construction and solutions for performance, power and Area (PPA). You will collaborate to drive clocking methodologies and “best known methods” to streamline PD work, come up with guidelines and checklists, drive execution, and supervise progress. You will need to communicate and drive the needs of PD and Clocking with multi-functional teams that will enable achieving the goals of the back-end design for the project.
Minimum Qualifications
BS + 10 years of relevant experience
Experience with ASIC integration including one or more of the following: Floorplanning, Clock and Power distribution, global signal planning, and I/O planning.
Experience with Floorplanning tools, P&R flows, and global timing verification Flows is required.
Preferred Qualifications
Experience with hierarchical design approach, top-down design, budgeting, timing and physical convergence.
Experience planning, implementing, and analyzing high-speed clock distribution networks from the root to leaf.
Exposure to different strategies for clock distribution including balanced trees, mesh, and forwarded clocks.
Ability to use critical clock metrics revolving around latency, skew, and variation to prevent and solve sophisticated cross-hierarchy clocking issues.
Experience planning and crafting test structures to evaluate clocking functionality and performance post Silicon. Background in engaging with Test teams pre/post Silicon to debug and analyze problems from a clocking perspective.
Experience integrating IP from both internal and external vendors and be able to specify and drive IP requirements in the physical domain.
Experience with Physical Design topics: multiple voltage and clock domains, ESD solutions, and mixed signal block integration.
Experience with large subsystem designs (>20M gates) with frequencies in excess of 1GHz applying brand new technologies.
Familiar with various process related design issues including Design for Yield and Manufacturability, multi Vt strategies and thermal Mgt.
Proven track record in solving complex PD and cross functional problems, driving results directly and or directing a team of engineers to innovate and execute on world class designs.
Understanding of GPU architecture and design units.