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Salary
≈ $199k – $367k per year (Estimated)
Location
In office (Beaverton)
Seniority
Staff · 10+ years exp
Visa
H-1B filings in 12 months: 6,350 · for this role: 1,366 · green card filings: 39

Confirmed on the employer's own hiring board on Nov 8, 2026. First seen by Alion on Jun 1, 2026. Apple scores A on the Alion truth index.

Overview
Company
Impact
Profile match
Apple is an American multinational technology company founded in 1976 by Steve Jobs, Steve Wozniak and Ronald Wayne, and headquartered in Cupertino, California. It designs and sells consumer hardware including the iPhone, Mac, iPad, Apple Watch, AirPods and Vision Pro, together with the operating systems and silicon that run them. A growing services division built around the App Store, iCloud, Apple Music, Apple TV+ and Apple Pay now contributes a large share of profit, making Apple one of the most valuable companies in the world.

At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a forward-thinking and especially motivated Analog Mixed Signal IP Integration Engineer! As a member of our dynamic group, you will have the rare and great opportunity to work on upcoming products that will delight and encourage millions of Apple’s customers every day!

Description

In this highly visible role, you will support the integration of 3rd party IP in the SOCs developed by Apple. Your job is to verify that the IP deliverables are meeting Apple's high quality standards and get flawlessly integrated. The role involves working closely with different cross-functional teams within Apple as well as with external vendors. Occasional travel might be required.

Minimum Qualifications

BS degree in technical subject area and a minimum 10 years relevant industry experience.

Preferred Qualifications

Experience with Verilog modeling and model validation is a plus

Experience with standards like PCI Express, MIPI, USB or DisplayPort is a plus

Excellent written and verbal communication skills

Strong initiative and ownership of responsibilities, productive, able to meet aggressive deadlines

Experience in RTL design, verification or integration

Deep knowledge and experience with front-end tools such as simulation, synthesis, lint, logic equivalence, static timing analysis, CDC, RDC, and UPF

Familiarity with SOC design flow and verification methodologies

Good understanding of DFT requirements for SOCs

Experience writing Verilog, SystemVerilog, SVA hardware description languages

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