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Confirmed on the employer's own hiring board on Nov 8, 2026. First seen by Alion on Nov 3, 2026. Apple scores A on the Alion truth index.

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Apple is an American multinational technology company founded in 1976 by Steve Jobs, Steve Wozniak and Ronald Wayne, and headquartered in Cupertino, California. It designs and sells consumer hardware including the iPhone, Mac, iPad, Apple Watch, AirPods and Vision Pro, together with the operating systems and silicon that run them. A growing services division built around the App Store, iCloud, Apple Music, Apple TV+ and Apple Pay now contributes a large share of profit, making Apple one of the most valuable companies in the world.

Imagine yourself at the center of our SOC/chip DV effort. Where we are collaborating with all fields, playing a meaningful role of getting functional products to millions of customers quickly. As the SoC Verification Engineer, we are responsible for taking part in a SoC verification process of a large scale SoC.

The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices - strengthening our dedication to leave the world better than we found it.

Join us!

Description

As a member of the verification team you will develop verification test plans, tools, test benches, protocol monitors, and high-coverage stimulus vectors.

You will apply sophisticated techniques to achieve verification with the highest quality, efficiency, and time-to-market

You are going to work closely with the design team to ensure timely delivery of quality designs

You will also work with methods to accelerate verification time

You will also be involved in Post Silicon Validation

Minimum Qualifications

You should have a BS/MS in Computer Engineering, Electrical Engineering, Computer Science, or equivalent experience.

Ability to fluently speak & write in English.

Preferred Qualifications

Hands-on experiences in SoC verification.

Knowledge of SoC architecture/design and in-depth knowledge of verification flow.

Strong understanding and proven experience in the sophisticated verification process, including dynamic, coverage-based and formal methods.

Experience using some of the following: Perl, e, Verilog, System Verilog, C, C++, TCL.

Familiarity with verification environments e.g. UVM, System Verilog is an advantage.

Knowledge in formal, hardware acceleration is a plus.

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