SoC Full Chip DV Engineer
Confirmed on the employer's own hiring board on Nov 15, 2026. First seen by Alion on Apr 10, 2026. Apple scores A on the Alion truth index.
Does making the next great technology product excite you? Imagine what you could do here. At Apple, our new insights have a way of becoming great products, services, and customer experiences very quickly. We bring passion and dedication to our job and when you are a part of that team there's no telling what we'll could accomplish. Design Verification Engineers at Apple are responsible for verifying the functionality and performance of Apple’s premier SOCs. This is a critical job within Apple's Hardware Technology, and we'd love to have you join us.
Description
As part of a very talented team, we are at the heart of the chip design effort collaborating with all fields (vertical product model)! You own ensuring the quality of the SOC or an IP or subsystem. This requires you to review design and architecture specifications and work closely with design & micro-architecture teams. A key component to the job is understanding the functional & performance goals of the design and you use this knowledge to test effectively. You develop test plans; tests & coverage plans as well as define our next generation verification methodology & test benches. It's required that you communicate and collaborate with design, architecture and software to understand the use cases and corner conditions and drive test cases. We also require additional responsibilities such as running and triaging regressions, tracking bugs, and analyzing coverage to achieve top results.
Minimum Qualifications
Minimum of BS + 3 years relevant industry experience.
Preferred Qualifications
Skilled in many aspects of digital verification such as constrained random verification process, functional coverage, code coverage, assertion methodology & philosophy
Knowledge of Verilog/SystemVerilog, digital simulation and debug
Knowledge of computer architecture and digital design fundamentals
Ability to work independently to deliver the project goals
Exposure to UVM is desired
Experience with C/C++, assembly is a plus
Experience with perl, python or similar scripting language
Excellent interpersonal skills and the dream to take on diverse challenges