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Salary
≈ $180k – $406k per year (Estimated)
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In office (Sunnyvale)
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Confirmed on the employer's own hiring board on Nov 11, 2026. First seen by Alion on Apr 29, 2026. Apple scores A on the Alion truth index.

Overview
Company
Impact
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Apple is an American multinational technology company founded in 1976 by Steve Jobs, Steve Wozniak and Ronald Wayne, and headquartered in Cupertino, California. It designs and sells consumer hardware including the iPhone, Mac, iPad, Apple Watch, AirPods and Vision Pro, together with the operating systems and silicon that run them. A growing services division built around the App Store, iCloud, Apple Music, Apple TV+ and Apple Pay now contributes a large share of profit, making Apple one of the most valuable companies in the world.

Come join Apple’s wireless silicon development effort, with its emphasis on highly energy-efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically coordinated engineering team.

Description

Develop MAC layer design for wireless communication SoCs, including creating microarchitecture and other documents based on system-level requirements, and writing area- and power-efficient RTL that is scalable. Work with systems and software teams to ensure performance and power efficiency. Collaborate with verification and emulation teams on debug, test plan review and code coverage closure. Run tools to ensure lint and CDC/RDC clean design. Work with synthesis team to review constraints, close timing and review area/timing reports.

Minimum Qualifications

BS in Electrical Engineering, Computer Engineering, or a related field.

Excellent understanding of digital logic design fundamentals.

Ability to translate functional requirements into synthesizable Verilog or SystemVerilog RTL.

Knowledge of digital design flows such as RTL simulation and debug, synthesis, lint, STA, and LEC.

Excellent organization skills.

Excellent communication skills - both written and oral.

Preferred Qualifications

Ability to design multi-clock-domain logic and resolve CDC problems.

Experience in ASIC microarchitecture and RTL design.

Understanding wireless standards, such as IEEE 802.11, 802.15, Bluetooth or 3GPP.

Understanding of ASIC low power design techniques, e.g. multiple supply domains configuration and management, dynamic power/clock scaling and power analysis is a plus.

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