Hardware & Digital High-Speed Simulation Engineer (w/m/d)
Confirmed on the employer's own hiring board on Nov 5, 2026. First seen by Alion on Nov 5, 2026. Avnet scores B on the Alion truth index.
TRIA
Tria, an Avnet company, gets your products to market faster, better and stronger with compute, system and HMI innovation. Our mission is to help OEM customers build user interface solutions that meet the future demand of innovation and quality with reduced time to market utilizing our platform technologies and design & manufacturing capabilities. Tria builds embedded compute, system and HMI solutions that meet the demand for innovation and quality, with reduced time to market, utilizing Tria’s platform technologies, design and manufacturing capabilities, and a world-class team of experts.
Principal Responsibilities:
- Design, develop, and validate complex embedded computing and industrial hardware platforms.
- Design and implement high-speed digital circuits and subsystems based on modern CPUs, SoCs, FPGAs, and advanced interconnect technologies
- Own the design and integration of high-speed interfaces including like DDR4 & DDR5 memory subsystems, PCI Express Gen4 & Gen5, USB 3.x & USB4, DisplayPort and High-speed Ethernet & SerDes-based interfaces
- Perform schematic capture, circuit design reviews, and support bring-up of complex multi-layer PCB designs.
- Define PCB stack-ups, routing constraints, and layout guidelines for high-speed designs.
- Perform and review Signal Integrity (SI) and Power Integrity (PI) simulations using industry-standard tools such as Cadence Sigrity or equivalent.
- Develop and execute pre-layout and post-layout simulation strategies, including eye-diagram analysis, jitter analysis, channel compliance, and power distribution network analysis.
- Collaborate closely with PCB layout engineers to optimize critical signal paths, impedance control, return current structures, and power distribution networks.
- Support electrical validation, debugging, root-cause analysis, and performance optimization in laboratory environments.
- Develop scripts and automation tools to improve simulation, analysis, and validation workflows.
- Support customer projects by providing simulation expertise, design reviews, technical recommendations, and issue resolution.
Job Level Specifications:
- Degree in Electrical-/ Computer Engineering or a related field with 5+ years of experience in high-speed digital design, simulation and digital hardware design
- Strong expertise in high-speed digital design and multi-layer PCB development
- Hands-on experience with High-speed SerDes technologies, SoCs with external memory interfaces and SI-/PI-Simulation with Cadence Sigrity or equivalent
- Strong understanding of Signal Integrity (SI), Power Integrity (PI), impedance control, timing budgets, crosstalk mitigation, and high-speed routing techniques
- Familiarity with the ECAD toolchain from Cadence, or similar platforms
- Experience in hardware debugging using oscilloscopes, protocol analyzers, TDR, VNA, and related laboratory equipment
- Strong analytical and problem-solving skills with the ability to solve complex hardware design challenges
- Excellent communication and teamwork skills
- Fluent in English; German is considered an advantage
The above statements are intended to describe the general nature and level of work being performed. They are not intended to be construed as an exhaustive list of all responsibilities, duties, and skills.
Avnet is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, or protected veteran status and will not be discriminated against on the basis of disability. If you are interested in applying for employment with Avnet and need special assistance or an accommodation to apply for a posted position contact our Human Resources Service Center in your region: Americas applicants - [email protected], Asia applicants -[email protected], EMEA applicants - [email protected].