379,843open jobs
9,927companies
47,741added this week
Browse all
Salary
$144k – $230k per year
Location
In office (Broomfield, San Diego, Fort Collins, San Jose, Irvine)
Seniority
Principal · 12+ years exp
Employment
Full-Time
Overview
Company
Impact
Profile match
Broadcom is an American semiconductor and infrastructure software company headquartered in Palo Alto, California, whose chip lineage runs back through Avago to the Hewlett-Packard components division. It designs networking switch and routing silicon that carries a large share of data centre traffic, custom AI accelerators built for hyperscale customers, plus wireless, broadband, storage and optical components. A sequence of very large acquisitions, culminating in the sixty-nine billion dollar purchase of VMware in 2023, has made infrastructure software roughly as important as chips to the group, and it is one of the most valuable listed technology companies in the world.

Please Note:

1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)

2. If you already have a Candidate Account, please Sign-In before you apply.

Job Description:

Design Verification Engineer

Broadcom's ASIC Products Division (APD), a worldwide leader in the design of complex custom ASICs and embedded IP, is looking for an experienced verification engineer that will be responsible for modeling and verification activities related to complex digital and mixed signal (MXS) IP blocks used in Broadcom’s ASIC developments.

The engineer will be responsible for defining verification plans and environment architecture, developing test cases and test bench components, coverage analysis and closure, and debug. This position may involve working with emulation and FPGA prototyping platforms and leading efforts in evaluating and driving the adoption of advanced verification methodologies/flows. The engineer will be expected to develop functional models to facilitate the block, system, and ASIC level verification. The candidate must work closely with the design teams and EDA vendors to accomplish the modeling and verification tasks.

The candidate must have experience using SystemVerilog and UVM, designing verification components including UVM agents, checkers, and behavioral models. Experience with implementing and achieving coverage goals by developing random & directed test cases, and SystemVerilog Assertions. This engineer will be responsible for analyzing and debugging simulation failures at the RTL and gate-level. The engineer must be knowledgeable of RTL, gate-level netlists, and SDF and capable of analyzing such formats in the verification context.

Requirements:

  • 12+ years of experience with verification concepts and architectures for complex digital and MXS circuits

  • Experience verifying designs at the block and system levels.

  • Experience with complex digital and mixed-signal circuits (PLL, DLL, ADC, DAC)

  • Experience debugging RTL and gate-level netlists, analyzing schematic diagrams of analog / MXS circuits

  • Experience using SystemVerilog and advanced verification concepts and methodologies (UVM, SVA)

  • Experience with Synopsys, Cadence, and Mentor simulations tools

  • Demonstrated ability to plan and deploy complex, reusable, and scalable verification environments

  • Experience with Perl/Python and Tcl or other scripting languages

  • Experience with version control systems (DesignSync, git)

  • Superior writing, grammar, and verbal communication skills

  • Excellent problem solver; develops and employs automated processes where applicable

  • Worked independently and in a global team and dynamic environment in a highly visible role

  • Possesses ability to learn and adapt to new tools and methodologies on the fly

  • Must have legal authorization to work in the US

It is a plus if the candidate has expertise in one or more of the following areas:

  • Experience with hardware design and debug

  • Experience with emulation (Palladium, Veloce, Zebu) and FPGA (Xilinx) platforms

  • Formal verification concepts / experience is a plus

  • Experience with verifying iJTAG network using ICL and PDL in the Tessent tool a plus

  • Experience with co-simulation a plus

Education and Experience required:

  • BS in Electrical Engineering / Computer Engineering and 12+ years of related experience; or an MS in Electrical Engineering / Computer Engineering and 10+ years of related experience.

Compensation and Benefits

The annual base salary range for this position is USD 143,800.00 To USD 230,000.00

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Free account
Stop reading job ads. Get the ones that fit.
One free account turns this page into a shortlist built around your stack, your level and your pay.
Match on every job. Stack, seniority, pay and location, scored against your profile.
379,843 open roles. Read straight off company career pages, refreshed every day.
Unlimited applications. Every one you send is tracked in one place, on-site or on a company board.
3 tailored CVs a month. Rewritten for the exact job you are applying to. Included free.
Create a free account
Free forever. No card. Under a minute.

Your match

How well do you fit this role?
Two answers are enough for a real match. No account needed.
Check my fit
Answers stay in this browser until you create an account.

Recommended for you based on this role

Similar stack
Same company
Broomfield
In office • Full-Time • 10+ years exp • Master's Degree • Tianjin
C++
Perl
Python
Chips/EDA
Synopsys TestMAX
Tessent
Apply
$125k – $172k per year • In office • Full-Time • 5+ years exp • Bachelor's Degree • San Diego
C++
Python
SystemVerilog
Verilog
VHDL
AI/ML
CNN
Reinforcement Learning
DevOps
Bitbucket
CI/CD
Git
Jenkins
Splunk
Apply
$46k – $108k per year (Estimated) • Remote • Full-Time • 5+ years exp • Associate's Degree • Germany
Bash
JavaScript
PHP
Python
DevOps
CentOS Stream
Hyper-V
Red Hat
Ubuntu
VMWare
Apply
$38k – $86k per year (Estimated) • In office • Full-Time • Bachelor's Degree • Gratkorn
C++
Python
Rust
Chips/EDA
OpenOCD
Apply
$120k – $203k per year • In office • Full-Time • 10+ years exp • Bachelor's Degree • Boston
Java
Python
DevOps
AWS
Docker
Incident Management
Apply
$129k – $207k per year • Equity • In office • Full-Time • 12+ years exp • Bachelor's Degree • Fort Collins
Apply
$122k – $195k per year • Equity • In office • Full-Time • 8+ years exp • Bachelor's Degree • San Jose
Apply
hardware engineer 5 3 days ago
$144k – $230k per year • Equity • In office • Full-Time • 12+ years exp • Bachelor's Degree • San Jose
Apply
$22k – $53k per year (Estimated) • In office • Full-Time • 3+ years exp • Bengaluru
Chips/EDA
Cadence Virtuoso
Apply
I/O Design Engineer 3 days ago
$81k – $194k per year (Estimated) • In office • Full-Time • 6+ years exp • Master's Degree • Singapore
Verilog
AI/ML
Edge AI
Chips/EDA
Cadence Virtuoso
Apply
$113k – $155k per year • In office • Full-Time • 5+ years exp • Bachelor's Degree • Broomfield
MATLAB
Apply
$90k – $147k per year • In office • Full-Time • 8+ years exp • Bachelor's Degree • Broomfield
AI/ML
Ray
Chips/EDA
Mentor PADS
Apply
$91k – $146k per year • Equity • In office • Full-Time • 8+ years exp • Bachelor's Degree • Broomfield
Python
DevOps
Azure
VMWare
Cybersecurity
Burp Suite
CVSS
GDPR
Microsoft Entra ID
Nessus
Qualys Cloud Platform
STRIDE
Threat Modeling
Apply
$112k – $140k per year • Equity • In office • Full-Time • 5+ years exp • High School Diploma • Broomfield
DevOps
AWS
Azure
Apply
$86k – $108k per year • Equity • Remote • Full-Time • 3+ years exp • High School Diploma • Broomfield
Perl
Python
DevOps
AWS
Azure
Cybersecurity
Wireshark
Web3
Layer 2
Apply
See all jobs
This is one of many
379,843 more open roles from verified company boards, updated every day.