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Salary
$30k – $78k per year (Estimated)
Location
In office (Shanghai)
Seniority
Principal
Employment
Full-Time
Overview
Company
Impact
Profile match
Broadcom is an American semiconductor and infrastructure software company headquartered in Palo Alto, California, whose chip lineage runs back through Avago to the Hewlett-Packard components division. It designs networking switch and routing silicon that carries a large share of data centre traffic, custom AI accelerators built for hyperscale customers, plus wireless, broadband, storage and optical components. A sequence of very large acquisitions, culminating in the sixty-nine billion dollar purchase of VMware in 2023, has made infrastructure software roughly as important as chips to the group, and it is one of the most valuable listed technology companies in the world.

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Job Description:

Broadcom Limited offers an excellent opportunity to contribute to a team environment and to grow personal career path. You will be working with internal and external customers to develop state of the art IC solutions utilizing Broadcom’s leading-edge CMOS cell-based ASIC technologies. You will have responsibility for ASIC designs through all of the key development and implementation phases including RTL analysis, synthesis, design optimization, timing verification, simulation, test insertion, physical design, vector generation, and post-prototype test support. Candidates will have opportunity to work on the latest 5nm/3nm designs

Detail design tasks include

Full Chip Synthesis and STA: An ideal candidate should have some background on full chip synthesis flow (DC, DCT, DCG) for 5nm/3nm design tape out. It would be better if the candidate have the experience running full chip STA and constraint clean up flow.

Physical Design Implementation: An ideal candidate having some background in either the Physical Design which includes floor planning, placement, design closure, and DRC & LVS skills.

Overall, candidates are expected to develop the most of above skills. Candidates who have the desire to seek the in-depth and broad technical challenge should apply.

Requirements/Qualifications

- Candidates should have good understanding about ASIC design flow and solid VLSI background.

- Candidates should be able to handle block implementation/top level task independently.

- Tapeout experience in 5nm and blow process design.

- Candidate s should have strong communications and problem solving skills.

- Candidates with experience in any one of following knowledge are a plus

- DFT insertion

- Power/IVD analysis

- DRC/LVS

- Top Floorplan/STA & Low Power

- Candidate is good at Perl/Tcl/Python

Education/Certifications

Preferred Degree: MS Preferred Major: Microelectronics or related discipline

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

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