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Salary
$144k – $230k per year
Location
In office (San Jose)
Seniority
Principal · 13+ years exp
Visa
H-1B filings in 12 months: 101 · green card filings: 23
Employment
Full-Time

Confirmed on the employer's own hiring board on Nov 13, 2026. First seen by Alion on Nov 12, 2026. Broadcom scores B on the Alion truth index.

Overview
Company
Impact
Profile match
Broadcom is an American semiconductor and infrastructure software company headquartered in Palo Alto, California, whose chip lineage runs back through Avago to the Hewlett-Packard components division. It designs networking switch and routing silicon that carries a large share of data centre traffic, custom AI accelerators built for hyperscale customers, plus wireless, broadband, storage and optical components. A sequence of very large acquisitions, culminating in the sixty-nine billion dollar purchase of VMware in 2023, has made infrastructure software roughly as important as chips to the group, and it is one of the most valuable listed technology companies in the world.

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Job Description:

We are seeking an experienced ASIC Implementation Engineer to drive physical design execution on next-generation, high-complexity system-on-chip (SoC) architectures across advanced FinFET process nodes (e.g., 5nm, 3nm, 2nm).

In this role, you will lead critical implementation disciplines-from floorplanning through to clocking, power integrity, and final timing signoff. You will work closely with architecture, RTL, CAD, and package engineering teams, as well as external foundry partners and customers worldwide, to ensure first-pass silicon success under demanding performance, power, and area (PPA) constraints.

  • Full-Flow Physical Implementation: Drive block- and top-level implementation flows, including floorplanning, placement, clock tree synthesis (CTS), routing, and post-route optimization.
  • Timing & Signal Integrity Closure: Perform static timing analysis (STA), crosstalk analysis, and signal integrity signoff across all PVT corners and operating modes.
  • Physical Verification: Execute DRC, LVS, antenna, and ERC checks, resolving complex multi-patterning and design-rule violations associated with advanced lithography.
  • Tool & Flow Optimization: Leverage and benchmark industry-standard EDA tool suites (Synopsys, Cadence, Siemens) to continuously enhance flow automation, runtime efficiency, and PPA metrics.
  • Cross-Functional Collaboration: Partner with geographically distributed teams, customers, and foundry interface teams to resolve implementation bottlenecks and adapt quickly to shifting project requirements.

Requirements:

  • BS Degree in Electrical Engineering and 13+ years related experience or MS in Electrical Engineering and 10+ years related work experience.

Compensation and Benefits

The annual base salary range for this position is USD 143,800.00 To USD 230,000.00

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

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