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Application Engineer - Physical Design (Back-End)

Cadence Design Systems · English · EDA Software · Semiconductor IP & Chip Design Services · Bachelor's Degree · 4 days ago

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Location

In office (Petah Tikva)

Seniority

Senior · 7+ years exp

Employment

Full-Time

Confirmed on the employer's own hiring board on Oct 29, 2026. First seen by Alion on Oct 25, 2026. Cadence Design Systems scores B on the Alion truth index.

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Cadence Design Systems

Cadence Design Systems is an American software company founded in 1988 that supplies the electronic design automation tools engineers use to design and verify integrated circuits. Its products cover digital synthesis and place-and-route, custom and analogue design, circuit simulation with the Spectre and Virtuoso families, functional verification, and increasingly system-level analysis for packaging, thermal behaviour and computational fluid dynamics. Headquartered in San Jose and listed on Nasdaq, it also licenses design intellectual property such as processor and interface blocks, and competes primarily with Synopsys and Siemens EDA.

cadence.com · HQ: San Jose, United States · Semiconductor IP & Chip Design Services · EDA Software · 5000+ employees · Est. 1988

Tech stack of Cadence Design Systems

Backed by Sequoia Capital

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

This is an excellent opportunity to work on challenging and complex projects at advanced technology environment with major companies in the semiconductor domain!

This role will enable you to improve your technical skills, working with the industry leading engineers over a wide range of topics while interacting with the business world.

The Application Engineer will provide expert level technical customer Pre-Sale and post-sale support for Cadence customers in Physical Design area.

Requirements:

BSc / MSc/ PhD in Electrical engineering from a leading institute.
7+ years of experience in Physical Design (back-end) digital implementation: floor planning, place and route, clockTree, STA
Experience in the Synthesis, Formal verification and DFT is an advantage.
Experience in microelectronics/ EDA industry.
High level of English.
Strong presentation and communication skills.

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