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Salary
≈ $93k – $169k per year (Estimated)
Location
In office (Austin)
Seniority
Middle · 2+ years exp
Visa
H-1B filings in 12 months: 368 · green card filings: 176
Employment
Full-Time

Confirmed on the employer's own hiring board on Oct 21, 2026. First seen by Alion on Sep 25, 2026. Cadence Design Systems scores B on the Alion truth index.

Overview
Company
Impact
Profile match
Cadence Design Systems is an American software company founded in 1988 that supplies the electronic design automation tools engineers use to design and verify integrated circuits. Its products cover digital synthesis and place-and-route, custom and analogue design, circuit simulation with the Spectre and Virtuoso families, functional verification, and increasingly system-level analysis for packaging, thermal behaviour and computational fluid dynamics. Headquartered in San Jose and listed on Nasdaq, it also licenses design intellectual property such as processor and interface blocks, and competes primarily with Synopsys and Siemens EDA.
Backed by Sequoia Capital

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

This person will work with the existing functional verification environment to add new features into the verification environment, ensuring various customer configurations are clean as part of verification regressions, supporting customers in case of any issues with using the verification environment, and functional and code coverage. Additionally, this person will be responsible for ensuring that the design is in line with the technical and quality requirements set for the team - particularly with respect to our quality Metrics.

The position is based in Austin.

Position Requirements:

  • BS/MS - Electrical / Computer Engineering
  • At least 2-3 years of relevant experience including design verification experience.
  • Strong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.
  • UVM based functional verification environment development is required.
  • AXI and/or CHI-E, DDR Memory experience is highly desirable.

Memory controller verification experience is desirable.

As a Verification Engineer for Memory Controller development team, you will lead the verification effort and contribute to the functional verification of the Cadence's Memory Controller IP. This person will work with the existing functional verification environment to add new features into the verification environment, ensuring various customer configurations are clean as part of verification regressions, supporting customers in case of any issues with using the verification environment, and functional and code coverage. Additionally, this person will be responsible for ensuring that the design is in line with the technical and quality requirements set for the team - particularly with respect to our quality Metrics.

The position is based in Austin.

Position Requirements:

  • BS/MS - Electrical / Computer Engineering
  • At least 2-3 years of relevant experience including design verification experience.
  • Strong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.
  • UVM based functional verification environment development is required.
  • AXI and/or CHI-E experience is highly desirable.

Memory controller verification experience is desirable.

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