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Firmware Engineer II

Cadence Design Systems • EDA Software • Semiconductor IP & Chip Design Services • Python • Verilog • Perl • TCL Scripting • 3 days ago
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Salary
≈ $34k – $79k per year (Estimated)
Location
In office (Beijing, Shanghai)
Seniority
Middle
Employment
Full-Time

Confirmed on the employer's own hiring board on Oct 18, 2026. First seen by Alion on Oct 15, 2026. Cadence Design Systems scores B on the Alion truth index.

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Cadence Design Systems

Cadence Design Systems is an American software company founded in 1988 that supplies the electronic design automation tools engineers use to design and verify integrated circuits. Its products cover digital synthesis and place-and-route, custom and analogue design, circuit simulation with the Spectre and Virtuoso families, functional verification, and increasingly system-level analysis for packaging, thermal behaviour and computational fluid dynamics. Headquartered in San Jose and listed on Nasdaq, it also licenses design intellectual property such as processor and interface blocks, and competes primarily with Synopsys and Siemens EDA.
cadence.com • HQ: San Jose, United States • Semiconductor IP & Chip Design Services • EDA Software • 5000+ employees • Est. 1988
Tech stack of Cadence Design Systems
Backed by Sequoia Capital

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Description

Be part of the Cadence DDR PHY IP Front End Design team responsible for -

  • Develop firmware for DDR5 PHY using microcontrollers
  • Developing firmware in C typically involving bare-metal programming and developing low-level APIs on Microcontrollers.
  • Responsible for collaborating with hardware designers and memory subsystem architects to derive training algorithms and implement them.
  • Responsible for collaborating with the verification team to deduce firmware-hardware co-verification plan.
  • Develop and Debug firmware in RTL based hardware simulations (C +Verilog simulations)
  • Develop and Debug on Silicon bring-up boards.

Required Skills:

  • Good Knowledge of DDR5 JEDEC spec, knowledge of different DIMM configurations and specifications.
  • Relevant experience in developing bare-metal firmware for High-speed SerDes or Memory interface Physical Layer blocks.
  • Good Knowledge of C programming language for embedded software development and use of relevant IDE.
  • Comfortable debugging RTL simulations involving firmware and microcontroller subsystem.
  • Good knowledge of Shell/Perl/Python/TCL scripting
  • Good experience on Verification EDA Tools like simulators and waveform viewers

We’re doing work that matters. Help us solve what others can’t.

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