Principal Design Engineer

Cadence Design Systems • Bachelor's Degree • Perl • SystemVerilog • Verilog • 1 year ago
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Salary
≈ $27k – $72k per year (Estimated)
Location
In office (Noida)
Seniority
Principal · 8+ years exp
Employment
Full-Time
Overview
Company
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Cadence Design Systems

Cadence Design Systems is an American software company founded in 1988 that supplies the electronic design automation tools engineers use to design and verify integrated circuits. Its products cover digital synthesis and place-and-route, custom and analogue design, circuit simulation with the Spectre and Virtuoso families, functional verification, and increasingly system-level analysis for packaging, thermal behaviour and computational fluid dynamics. Headquartered in San Jose and listed on Nasdaq, it also licenses design intellectual property such as processor and interface blocks, and competes primarily with Synopsys and Siemens EDA.
cadence.com • HQ: San Jose, United States • Hardware • Simulation & Digital Twin • EDA • Semiconductors • Software • 5000+ employees • Est. 1988

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Responsibilities

  • Design Verification for interconnect IP
  • Relevant experience in interconnect and subsystems is strongly preferred
  • Crafting verification plans and executing on those plans to verify highly complex and configurable designs.
  • Responsible for coverage collection and closure
  • Work closely with cross functional teams (DV/Arch/Design/FW) to identify coverage scope

Required Skills and Experience:

  • 8+ years of design verification experience
  • BS (or higher) in EE/Computer Engineering
  • Strong technical and interpersonal skills
  • Excellent knowledge of Interconnects, NoCs and design verification fundamentals.
  • Thorough understanding of System Verilog, UVM, and other programming languages to build flexible and reusable complex testbenches
  • Experience with development of fully automated flows
  • Exposure to scripting languages like Perl, Unix shell or similar languages
  • Experience with Formal Verification will be a plus
  • Experience with Gate Level Simulations
  • Excellent written and oral communication skills necessary

We’re doing work that matters. Help us solve what others can’t.

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