Salary
≈ $113k – $257k per year (Estimated)
Location
In office (Brussels)
Seniority
Principal · 8+ years exp
Employment
Full-Time
Confirmed on the employer's own hiring board on Nov 1, 2026. First seen by Alion on Nov 6, 2024. Cadence Design Systems scores B on the Alion truth index.
Overview
Company
Impact
Profile match
Cadence Design Systems is an American software company founded in 1988 that supplies the electronic design automation tools engineers use to design and verify integrated circuits. Its products cover digital synthesis and place-and-route, custom and analogue design, circuit simulation with the Spectre and Virtuoso families, functional verification, and increasingly system-level analysis for packaging, thermal behaviour and computational fluid dynamics. Headquartered in San Jose and listed on Nasdaq, it also licenses design intellectual property such as processor and interface blocks, and competes primarily with Synopsys and Siemens EDA.
Backed by Sequoia Capital
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Performance Modeling Engineer
Location - India (Pune)
Summary
We are looking for modeling engineers to help develop performance models, perform architectural tradeoff analysis, and enable data driven design decisions for our next generation DDR memory controller architectures that can meet today’s complex SoC and workload requirements. Hardware modelling experience (C++/SystemC/TLM/Python) and computer architecture foundation is desired.
Responsibilities
- Develop cycle-level performance models in SystemC or C++
- Correlate performance models to match RTL configurations and traffic conditions
- Work with Memory Architects to understand feature requirements, architectural specifications and implement in the model
- Analyze architectural trade-offs (throughput, hardware cost) across different scenarios and architectural choices
- Develop synthetic memory traffic/traces that are representative of real-world applications (CPU, GPU, DSP, NoC, etc)
- Develop scripts to automate generation of various performance metrics and statistics post RTL simulation that helps identify performance bottlenecks
Required Skills
- BE/B.Tech ME/M.Tech in ECE, E&TC, CS or similar
- 8+ years of experience in hardware modeling, functional or performance
- Strong coding skills in C++, SystemC and Transaction Level Modeling (TLM)
- Basic understanding of performance principles, Queuing Theory, throughput/latency tradeoffs
Additional Skills
- Understand RTL-Verilog, SV, UVM and experience analyzing waveforms
- Understand memory protocols and timing - DDR4, DDR5, LP4, LP5
- Experience using performance simulators - Memory Controller, NoC, CPU models
- Coding in Python and familiarity with packages like Pandas, Matplotlib
- Experience working with performance benchmarks - SPEC, STREAM, etc
- Concepts related to Quality of Service (QoS) and how memory controller can tradeoff performance and latencies
We’re doing work that matters. Help us solve what others can’t.
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