Location
In office (Austin)
Seniority
Principal · 8+ years exp
Visa
H-1B filings in 12 months: 368 · for this role: 61 · green card filings: 176
Employment
Full-Time
Confirmed on the employer's own hiring board on Nov 14, 2026. First seen by Alion on Nov 13, 2026. Cadence Design Systems scores B on the Alion truth index.
Overview
Company
Impact
Profile match
Cadence Design Systems is an American software company founded in 1988 that supplies the electronic design automation tools engineers use to design and verify integrated circuits. Its products cover digital synthesis and place-and-route, custom and analogue design, circuit simulation with the Spectre and Virtuoso families, functional verification, and increasingly system-level analysis for packaging, thermal behaviour and computational fluid dynamics. Headquartered in San Jose and listed on Nasdaq, it also licenses design intellectual property such as processor and interface blocks, and competes primarily with Synopsys and Siemens EDA.
Backed by Sequoia Capital
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Job Description
We are looking for a Principal Application Engineer responsible for providing pre-sales and post-sales technical support for the Digital Implementation and Signoff tools. The candidate will work closely with sales executives in supporting sales campaigns by delivering workshops, benchmarks, product demonstrations, methodology consultations and product support.
Position also involves:
- Presenting to customers the technical capabilities of Cadence Digital Implementation and Signoff tools and flows (Synthesis, Place and Route, Timing/Physical/Power Signoff).
- Recognizing opportunities for products at existing customers or potential customers, and working with account team to define and execute technical campaigns
- Support technical evaluations/benchmarks and drive the process to deliver Cadence solutions implementations
- Ongoing support and usage proliferation at existing customers (on/offsite)
- Working closely with R&D on tools and methodology improvements
- Create and contribute technical content for Cadence Online Support
- Travel as required (up to 20%)
The Position Requirements are …
- Minimum BS-EE plus 8 to 10 year’s experience or MS-EE, plus 6 to 8 year’s experience, Core timing signoff expertise, advanced node STA, UPF & constraints debugging, hierarchical & 3DIC design STA and closure solutions
- Digital Design Fundamentals, Semiconductor fundamentals and Static Timing Analysis is required
- Experience with ASIC digital implementation flows and tools
- Working knowledge of a scripting language TCL/Perl/Python
- Candidate should have strong customer-facing communication and problem solving skills
- Strong personal drive for continuous learning and expanding professional skill sets
- Strong verbal and written communication skills
We’re doing work that matters. Help us solve what others can’t.
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