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Salary
$151k – $278k per year (Estimated)
Location
In office (Austin)
Seniority
Principal · 8+ years exp
Employment
Full-Time
Overview
Company
Impact
Profile match
Cadence Design Systems is an American software company founded in 1988 that supplies the electronic design automation tools engineers use to design and verify integrated circuits. Its products cover digital synthesis and place-and-route, custom and analogue design, circuit simulation with the Spectre and Virtuoso families, functional verification, and increasingly system-level analysis for packaging, thermal behaviour and computational fluid dynamics. Headquartered in San Jose and listed on Nasdaq, it also licenses design intellectual property such as processor and interface blocks, and competes primarily with Synopsys and Siemens EDA.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

This opportunity is for a Product Engineer in the Digital and Signoff Group (DSG) at Cadence. The Cadence Digital and Signoff Group will offer you a dynamic environment in which you will work with innovative R&D and Customer Engagement teams to influence the development of software tools for advanced chip design platforms. As Product Engineer, you will be a source of technical place and route expertise to Cadence customers and to R&D.

You are a motivated and energetic engineer with a deep understanding of ASIC design methodologies and of every stage of the RTL to GDSII flow.

You have proven hands-on experience with timing closure and PPA optimization at 16nm and below nodes.

You combine your deep understanding with strong analysis skills to debug customer problems and propose solutions, with an organized and coherent approach.

You are an excellent communicator.

Position Responsibilities:

Support Cadence products in the Digital and Signoff team.

Track and debug customer issues and work with R&D and release team on issue resolution.

Run design benchmarks and develop flows and solutions.

Position Requirements:

MS in EE with 5+ years of experience in Digital Implementation, either as a design engineer or as a product engineer

Or BS in EE with 8+ years of experience in Digital Implementation, either as a design engineer or as a product engineer

Strong understanding of VLSI physical design and timing analysis; familiarity with digital implementation challenges including RTL synthesis, placement optimization, clock tree synthesis, routing optimization and silicon signoff.

Experience with industry standard EDA tools in Synthesis, Physical design and Signoff at 16nm and below nodes.

Exposure to, and solid understanding of, hierarchical design methodologies and low power design

Energetic team player with a passion for problem solving

Strong analysis skills with a track record to prove it

Strong communication skills (verbal and written)

Automation skills using Perl, Tcl and shell scripting

We’re doing work that matters. Help us solve what others can’t.

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