Senior Principal Design Engineer
Confirmed on the employer's own hiring board on Oct 31, 2026. First seen by Alion on Oct 12, 2026. Cadence Design Systems scores B on the Alion truth index.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Job Responsibilities:
Focus on high-speed interface PHY IP physical implementation, develop necessary scripts or tools to enhance current PD design flow. Work in product projects, including but not limited to: complete the project tasks; solve design issue and provide flow to check and avoid similar issue; analyze and summarize PPA optimization methodologies and results, implement optimal design parameters and flows for different projects.
Job Requirement:
-BS with minimum 9+ years of experience. MS with minimum 7+ years of experience.
-Strong physical design experience in the digital implementation domain including Floorplan, CTS, STA, Physical verification, Power analysis.
-Solid background in circuits, electronics, physics, be willing to learn new technology for cutting edge process node and advanced design methodology.
-Skilled in scripting language, such as Perl, C shell, TCL, Makefile, Python.
-Familiar with EDA tools like Innovus, ICC, Calibre, Tempus, PrimeTime, etc.