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Software Engineer II

Cadence Design Systems • EDA Software • Semiconductor IP & Chip Design Services • Master's Degree • C++ • 2 days ago
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Location
In office (Hsinchu)
Seniority
Middle
Employment
Full-Time

Confirmed on the employer's own hiring board on Oct 14, 2026. First seen by Alion on Aug 18, 2026. Cadence Design Systems scores B on the Alion truth index.

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Cadence Design Systems

Cadence Design Systems is an American software company founded in 1988 that supplies the electronic design automation tools engineers use to design and verify integrated circuits. Its products cover digital synthesis and place-and-route, custom and analogue design, circuit simulation with the Spectre and Virtuoso families, functional verification, and increasingly system-level analysis for packaging, thermal behaviour and computational fluid dynamics. Headquartered in San Jose and listed on Nasdaq, it also licenses design intellectual property such as processor and interface blocks, and competes primarily with Synopsys and Siemens EDA.
cadence.com • HQ: San Jose, United States • Semiconductor IP & Chip Design Services • EDA Software • 5000+ employees • Est. 1988
Tech stack of Cadence Design Systems
Backed by Sequoia Capital

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Placement Team (Cadence Innovus)

Job Description

As a member of our Placement Team, you will design, develop, maintain, and enhance our cutting-edge detailed placement technologies. You will work at the forefront of advanced semiconductor design, developing lithography-driven placement solutions for leading-edge process nodes.

The primary responsibility of this role is to design, develop, troubleshoot, and debug software applications on Unix/Linux platforms.

Core Responsibilities

  • Lead the development and maintenance of core placement algorithms.
  • Design, implement, and enhance advanced placement technologies and methodologies.
  • Collaborate with the Routing and OPT teams to define and develop next-generation algorithms.
  • Conduct peer code reviews and maintain high standards for code quality, scalability, thread safety, and test coverage.
  • Work closely with cross-functional teams to improve solution quality, performance, and usability.

Requirements

  • Strong software development skills in C/C++.
  • Solid understanding of QoR (Quality of Results) and PPA (Performance, Power, and Area) optimization.
  • Proven experience with EDA back-end design flows, including placement, timing analysis, optimization, and routing.
  • Strong interest in and understanding of developing complex software systems on Unix/Linux platforms.
  • Excellent verbal and written communication and presentation skills.
  • Experience working with TSMC and semiconductor design companies is a strong plus.
  • M.S. degree in Electrical Engineering, Computer Science, or a related field required; Ph.D. preferred.

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