校招 北京-RTL Design Engineer (Memory & Interconnect)
Confirmed on the employer's own hiring board on Nov 12, 2026. First seen by Alion on Nov 11, 2026.
岗位职责 / Responsibilities
Core Responsibilities
Use AI tools across the digital IC front-end flow; integrate automated agents into design flows and continuously optimize.
Drive microarchitecture design, iteration, and RTL implementation for memory subsystems and data movement.
Perform functional evaluation and performance analysis; support pre-simulation verification.
任职要求 / Requirements
Requirements
Master’s or above in Electronics, Computer Science, or related fields.
Basic Verilog/SystemVerilog and digital circuit fundamentals.
No prior experience required; digital IC project experience is a plus. Learning ability, logical thinking, and technical potential are valued more.
Preferred
Knowledge/experience in memory controllers (DDRC, HBM_Ctrl, 3DDRAM), interconnect (NoC), or AI chips.
Good communication, teamwork, and fluent English.
AI enthusiast who actively uses AI tools for coding and verification; curious and adaptable to new flows, including LPU dataflow chips.
What We Offer
1:1 mentorship from senior experts; unrestricted access to world-leading AI tools; work on world-class AI chips.
Join core projects from day one: full front-end flow with AI agents, block-level microarchitecture/RTL, and C model build/test for architecture exploration.