AI Accelerator Chip Architect

Capgemini • Cybersecurity • Government • 1 month ago
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Salary
≈ $30k – $75k per year (Estimated)
Location
In office (Bengaluru)
Seniority
Architect · 15+ years exp
Employment
Full-Time

Confirmed on the employer's own hiring board on Oct 18, 2026. First seen by Alion on Sep 2, 2026. Capgemini scores B on the Alion truth index.

Overview
Company
Impact
Profile match

Capgemini

Capgemini is a French information technology services and consulting group founded in Grenoble in 1967 by Serge Kampf, and one of the largest IT service providers in the world. It designs, builds and runs systems for large enterprises and governments across some fifty countries, with a delivery workforce concentrated in India and a European client base heavier than most of its competitors. The group is organised into Capgemini Invent for strategy and design, Capgemini Engineering for research and development services acquired with Altran, and Sogeti for local technology services, and it has reoriented its portfolio around cloud migration, data platforms and generative AI.
capgemini.com • HQ: Paris, France • Management Consulting • Engineering Services • Systems Integrators • IT Consulting & Digital Transformation • 5000+ employees • Est. 1967
Tech stack of Capgemini
Backed by Bordeaux Technowest, Gilde Equity Management

Roles & Responsibilities

Lead architecture and technical strategy for AI/ML acceleration silicon, including compute engines, memory architecture, interconnects, and software enablement.

Key Responsibilities:

  • Define AI accelerator architecture.Analyze AI workloads and mapping strategies.
  • Drive NPU/Matrix Engine/MAC architecture decisions.
  • Define memory hierarchy and bandwidth requirements.
  • Guide RTL and verification teams.
  • Support customer technical workshops and solution definition.
  • Drive accelerator roadmap and differentiation.

Our Ideal Candidate

  • 15+ years in ASIC/SoC design.
  • Prior experience on AI, GPU, DSP, NPU, TPU, or HPC silicon.
  • Strong understanding of AI workloads and inference pipelines.
  • Experience in compute architecture and memory systems e.g. ARM Neoverse, RISC-V mesh based compute sub-system
  • Compute Sub-system experience
  • Complex NoC experience e.g. Arteris / ARM
  • Understanding on other processor such as ARM A, M and R series
  • Understanding of RTL design and verification.
  • Performance modeling experience and assessment using virtual or emulation platform.
  • Strong customer-facing capability.
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