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Salary
≈ $47k – $97k per year (Estimated)
Location
Hybrid (Greece)
Seniority
Architect
Employment
Full-Time

Confirmed on the employer's own hiring board on Oct 13, 2026. First seen by Alion on Sep 11, 2026. Capgemini scores B on the Alion truth index.

Overview
Company
Impact
Profile match
Capgemini is a French information technology services and consulting group founded in Grenoble in 1967 by Serge Kampf, and one of the largest IT service providers in the world. It designs, builds and runs systems for large enterprises and governments across some fifty countries, with a delivery workforce concentrated in India and a European client base heavier than most of its competitors. The group is organised into Capgemini Invent for strategy and design, Capgemini Engineering for research and development services acquired with Altran, and Sogeti for local technology services, and it has reoriented its portfolio around cloud migration, data platforms and generative AI.

Job Description

As a Senior RTL / SoC Functional Safety Engineer, you will play a key role in the development of complex ASIC and SoC solutions, with a strong focus on RTL design, Functional Safety, and system-level integration.In this role you will:

  • Design and implement hardware functionality using RTL (Verilog/SystemVerilog) as the primary development language.
  • Develop and integrate Functional Safety mechanisms at RTL and SoC level in compliance with ISO 26262 requirements.
  • Translate safety requirements into RTL implementations and ensure traceability from requirements to implementation and verification.Configure, integrate, and customize internal and third-party IPs within complex SoC environments.
  • Own and support IP configuration activities, including parameterization, feature enablement, interface configuration, and safety-related settings.
  • Create, maintain, and review IP-level technical documentation, including configuration specifications, integration guidelines, safety assumptions, limitations, and implementation details.
  • Document Functional Safety aspects for each IP, including safety requirements, safety mechanisms, diagnostic features, dependencies, and integration constraints.
  • Work with both internally developed and Black Box IPs, understanding integration, safety, and verification implications.
  • Contribute to SoC architecture definition, subsystem design, and RTL microarchitecture development.
  • Collaborate with Functional Safety, Verification, Design, and System teams to ensure successful implementation of safety requirements.Support fault analysis, safety reviews, and Functional Safety work products throughout the development lifecycle.
  • Participate in silicon development activities from architecture and implementation through integration and product delivery.
  • Consider system-level design aspects, including SoC interactions with PCB-level environments.

Your role

  • Strong experience in ASIC and/or SoC development, gained through successful contributions to complex semiconductor projects.
  • Solid hands-on expertise in RTL design and development using Verilog/SystemVerilog.
  • Experience with System-on-Chip (SoC) architecture, integration, and subsystem development.
  • Practical experience applying Functional Safety principles and ISO 26262 within semiconductor or safety-critical hardware development.
  • Experience implementing, integrating, and documenting safety mechanisms at RTL and system level.
  • Experience with IP integration, IP configuration, and IP customization within complex SoC environments.
  • Ability to create and maintain IP documentation, integration documentation, design specifications, and Functional Safety-related documentation.
  • Understanding of safety requirements allocation to IPs and the documentation required to support safety compliance.
  • Experience working with Black Box IPs and understanding their integration, verification, and safety considerations.
  • Knowledge of CPU architectures such as ARM and/or RISC-V.
  • Familiarity with on-chip communication protocols and interconnects such as AXI and NoC.
  • Understanding of hardware/software interaction within embedded systems.
  • Knowledge of hardware diagnostic concepts, fault detection mechanisms, redundancy schemes, and safety monitoring architectures.
  • Understanding of system-level hardware design considerations, including PCB integration and board-level interactions.
  • Strong communication and stakeholder management skills, with the ability to work effectively in cross-functional engineering teams.

What You'll Love About Working Here

Scale & Impact: Lead engagements with significant budgets, international teams, and strategic business impact.

Career Growth: Progress through Capgemini’s Engagement Management Certification, from Foundation to elite levels like Club d’Expert.

Learning & Development: Access to dedicated Engagement Manager Curriculum, executive-level training, and personalized learning via our digital platforms. Learn the best and latest work we are developing in Gen AI and Business AI.

Community & Support: Join a global network of 16,000+ Engagement Managers, with local meetups, global events, and peer mentoring.

Flexibility & Balance: Hybrid working policies allow you to manage your time and your work base effectively.

Make it real.

Capgemini is an AI-powered global business and technology transformation partner, delivering tangible business value. We imagine the future of organizations and make it real with AI, technology and people.With our strong heritage of nearly 60 years, we are a responsible and diverse group of over 420,000 team members in more than 50 countries. We deliver end-to-end services and solutions with our deep industry expertise and strong partner ecosystem, leveraging our capabilities across strategy, technology, design, engineering, and business operations.The Group reported 2025 global revenues of €22.5 billion.|www.capgemini.com

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