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Salary
$84k – $208k per year (Estimated)
Location
In office (Westminster)
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Intern
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CesiumAstro is an American company founded in Austin in 2017 that builds active phased array communications payloads for satellites, aircraft and defence platforms. Its systems are software-defined and electronically steered, which lets a moving platform track several links at once without mechanical antennas, and the company manufactures them in house rather than integrating third-party subsystems. It sells mainly to defence customers and satellite operators, has raised venture funding from investors including Airbus Ventures and Lightspeed, and operates facilities in Austin, Colorado and the United Kingdom.

The CesiumAstro hardware team is looking for Summer 2027 interns to develop HDL-level FPGA systems for satellite communication systems.

FPGA development interns will work closely with CesiumAstro engineers on FPGA circuits and systems through all phases of the development process. Areas of focus will include design, verification, testing, and deployment at the HDL level. FPGA HDL designs will include high-speed serial interfaces and data streams, digital processing cores, multiple clock domains, and management interfaces. Testing, validation, and verification will also be central tasks for any FPGA design. Assignments will be determined by a mix of project availability and the interests of the successful candidates.

CesiumAstro interns regularly present their work to peers, mentors, and CesiumAstro executive leadership throughout the course of the summer. As such, excellent written and verbal communication skills are required.

To apply, please include a cover letter describing your interest in FPGAs and either space systems or communication systems, as well as your status as a US citizen or permanent resident.

JOB REQUIREMENTS AND MINIMUM QUALIFICATIONS

  • Current enrollment in a Bachelor of Science (BS), Master of Science (MS), or PhD program in Electrical Engineering or Computer Engineering from an accredited university.
  • GPA of 3.5 or higher.
  • Advanced coursework in design, analysis, and implementation of FPGA systems at the HDL level.
  • Practical experience designing and building FPGA systems for a research project, competition team, extracurricular activity, or advanced engineering course.
  • Experience with FPGA design and verification (Verilog/VHDL, HDL coder, Xilinx’s Vivado, Modelsim, etc.).
  • Hands-on experience with lab instruments such as digital oscilloscopes, spectrum analyzers, RF signal generators, and vector signal analyzers.
  • Excellent written and verbal communication skills.

PREFERRED EXPERIENCE

  • Experience in digital signal processing.
  • Experience with board-level hardware design.
  • Advanced coursework in communication systems.
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