2027 Internship - Formal Verification Engineer

Cirrus Logic is seeking an intern candidate for our Formal Verification team in Austin, TX. This position is focused on applying Formal Verification to digital designs. It is available to students currently enrolled in a MS or PhD program in Electrical and Computer Engineering. Candidate must be available for full-time employment during the internship.

Responsibilities

• Support the formal verification team to follow, and improve, defined methodology practices.
• Develop test plans and verification methodologies to formally verify the microarchitecture and design.
• Perform failure analysis and resolution, coverage analysis, and population.
• Implement and improve functional and formal verification.

Required Skills and Qualifications:

• Master’s or PhD degree in Electrical or Computer Engineering
• Knowledge in designing and implementing verification environments for module-level designs.
• Excellent communication skills and a collaborative approach to working with team members.
• Proficiency in System Verilog.
• Familiarity with scripting languages such as Python, Perl, TCL, Bash.
• Experienced or knowledge in UVM or equivalent methodologies.
• Knowledge in formal property languages such as SVA.
• Knowledge in property-based model-checking.
• Knowledgeable in signal processing, analog or digital design fundamentals.