ESD Engineer

The ESD Engineer will drive the development of our I/O library-leading the design, simulation, characterization, and validation of advanced I/O pad structures. You’ll define and implement our chip- and IP-level ESD methodology, ensuring every product meets the highest standards of robustness and reliability.

In this role, you’ll design ESD protection devices, create silicon test structures for ESD and latch-up evaluation, and translate silicon data into optimized design rules. You’ll also collaborate closely with our foundry partners on ESD library updates and LUP rule development.

Success requires a holistic understanding of mixed-signal CMOS ESD/EOS protection, along with the ability to see gaps, integrate methodologies, and strengthen our end-to-end protection strategy. This is a high-impact opportunity to shape product reliability across Cirrus Logic’s entire mixed-signal portfolio.

Responsibilities

• Design, simulate, and optimize advanced I/O circuits and ESD protection structures.
• Characterize and model I/O libraries to support high-performance mixed-signal design flows.
• Release, maintain, and improve I/O libraries and models used across multiple design teams.
• Apply deep expertise in ESD and latch-up requirements to ensure robust, reliable silicon.
• Drive ESD sign-off for both chip-level and block-level designs, ensuring consistent methodology.
• Act as a technical leader, unifying ESD, latch-up, and I/O strategies-gaining alignment across business units and elevating best practices company-wide.

Required Skills and Qualifications

• MSc in Electrical Engineering (or equivalent experience) with a strong track record in advanced circuit design.
• A holistic understanding of ESD/EOS protection for mixed-signal CMOS circuits.
• Strong fundamentals in ESD circuit design, layout, and testing.
• Proven experience in I/O design, including CMOS circuitry, latch-up mitigation, physical verification, and device-level characterization.
• Chip-level ESD signoff expertise and a deep understanding of reliability requirements.
• Ability to guide layout engineers, ensuring robust, ESD-safe layout implementation.
• Proficiency with Cadence schematic capture, layout, and simulation tools.
• Ability to work independently as well as lead or collaborate within high-performing technical teams.
• Clear, effective communication-both written and verbal.
• Experience in IBIS model generation is a plus