ASIC Design Verification Engineer || Verilog, UVM, Testbench | Simulation || Exp 7+ years

Meet The team :

Silicon one group delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We craft the networking hardware for Enterprises and Service Providers, the Public Sector, and Non-Profit Organizations across the world.

Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio.

Come join us and take part in shaping Cisco's ground-breaking solutions by crafting, developing and testing some of the most sophisticated ASICs being developed in the industry. You will engage in dynamic collaboration with verification engineers, designers, and multi-functional teams, working together to ensure the successful verification of the ASIC throughout its lifecycle.

Your Impact :

As a Design Verification Engineer specializing in Simulation, you will be responsible for developing and executing verification strategies to ensure the correctness and performance of complex hardware designs. Your primary focus will be on emulation platforms to accelerate verification cycles and improve coverage.

Key Responsibilities:

• Develop and implement verification plans and test benches using Simulation tools and methodologies.
• Collaborate with design and validation teams to identify verification requirements and coverage goals.
• Utilize emulation platforms to run large-scale verification tests and debug design issues.
• Analyse verification results, identify bugs, and work closely with design engineers to resolve issues.
• Maintain and enhance verification infrastructure and automation frameworks.
• Document verification processes, test cases, and results to ensure traceability and reproducibility.
• Stay current with emerging verification technologies and best practices, particularly in emulation.
• Mentor junior engineers and contribute to team knowledge sharing.

Minimum Qualifications:

• Bachelors + 7 years of related experience, or Masters + 4 years of related experience, or PhD + 1 year of related experience
• Strong experience in Desiverification methodologies using UVM or OVM
• Relevant experience in design verification with a strong emphasis Test Methodologies
• Experience into Networking (Ethernet , AXI, AMBA, Pcie etc)

Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.

Disclaimer

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