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Salary
$16k – $34k per year (Estimated)
Location
Remote/Hybrid (Armenia)
Seniority
Junior · 2+ years exp
Employment
Full-Time
Overview
Company
Impact
Profile match
Cisco Systems is an American networking company founded in 1984 by Stanford computer scientists Leonard Bosack and Sandy Lerner, and headquartered in San Jose, California. It is the largest supplier of enterprise networking equipment in the world, building the routers, switches, wireless access points and optical systems that carry traffic across corporate networks, service providers and data centres, together with the software and silicon that run them. The company has diversified heavily into security, observability through Splunk, collaboration with Webex, and AI infrastructure networking, and now earns a growing share of revenue from software subscriptions rather than hardware sales.

This is a hybrid role with four days per week at Cisco’s Yerevan office.

Meet the Team

Join Cisco’s ASIC Design for Test (DFT) Team, where innovation, collaboration, and technical excellence drive everything we do. As a group of passionate engineers, we are committed to pushing the boundaries of testability and reliability in complex silicon systems. Our mission is to enable robust, high-quality silicon by architecting and implementing advanced DFT solutions. Working in close partnership with design, verification, and physical implementation teams, we ensure that every Cisco chip is not only powerful, but also rigorously tested and dependable. Here, you’ll play a pivotal role in shaping the future of test engineering while growing alongside some of the best minds in the industry.

Your Impact

In this role, you will be central to Cisco’s silicon quality and innovation by developing advanced DFT strategies that ensure every chip meets the highest standards for testability and reliability. You will address challenges across digital and mixed-signal domains, collaborating with multi-functional teams to design, implement, and optimize sophisticated test solutions. Your work will enhance product robustness, accelerate silicon validation, and drive progress in automated test methodologies.

  • Architect and Implement DFT Solutions: Design and integrate advanced Test Access Mechanisms (TAM), scan chains, Built-In Self-Test (BIST), and Memory BIST (MBIST) infrastructures for complex integrated circuits.

  • Test Planning and Coverage Analysis: Lead test planning, test pattern generation, and fault coverage analysis to improve test coverage for both digital and mixed-signal designs.

  • Collaborate Across Teams: Work closely with design, verification, ATE, and physical design teams to ensure DFT structures meet functional, timing, and implementation requirements.

  • Leverage Tools and Automation: Apply and develop automation scripts and in-house tools for DFT workflows, including MBIST pattern generation and fault simulation, using industry-standard EDA solutions.

  • Fault Diagnosis and Debugging: Identify, analyze, and debug issues related to DFT structures, perform root cause analysis on failed tests, and recommend design changes for improved testability.

  • Documentation and Reporting: Prepare detailed documentation on test plans, test coverage, and debugging results; report on DFT metrics to ensure compliance with company and industry standards.

Minimum Qualifications

  • Bachelor’s or higher degree in Electrical Engineering, Computer Engineering, or a related technical field.

  • 2+ years of hands-on experience in MBIST, SCAN/ATPG, and DFT methodologies for complex digital and mixed-signal designs.

  • Proven expertise with industry-standard DFT tools and flows (e.g., Synopsys, Cadence, Mentor).

  • Strong understanding of ASIC/FPGA design flow, including RTL design, verification, and test.

  • Proficiency in scripting languages such as Tcl, Python, or Perl for test automation and workflow enhancement.

  • Demonstrated ability to identify, analyze, and resolve DFT issues related to MBIST insertion, pattern generation, and fault coverage.

  • Excellent communication skills and experience collaborating within cross-functional engineering teams.

Preferred Qualifications

  • Expertise in advanced DFT methodologies such as Logic BIST, Memory BIST, and hybrid scan/MBIST approaches.

  • Experience with low-power DFT strategies and power-aware test techniques.

  • Ability to develop custom scripts or internal tools for DFT analysis and automation.

  • Familiarity with industry standards such as IEEE 1149.1 (JTAG) and IEEE 1500.

  • Experience leading DFT efforts on large-scale projects and mentoring junior engineers.

  • Strong project management skills and a track record of driving test planning and implementation best practices.

Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.

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