Senior Staff ASIC Design Engineer

As a Senior Staff ASIC Design Engineer, you will be responsible for all aspects of front-end ASIC design, including RTL implementation and verification of complex logic blocks. You will collaborate with PD, DFT, STA, and integration teams to ensure successful tape-outs and work closely with system teams for chip bring-up and validation.

Base salary range is $160,000 - $230,000 a year. The base salary offer will depend on factors such as education, experience, training, skills, qualifications, and location. This position is also eligible for a discretionary bonus, equity and a full range of medical and other benefits.

Why Credo

• Purpose: We invest in what matters. From meaningful-future shaping projects to competitive compensation, we empower you to grow your career while making a lasting impact.
• People: Connection starts within. We collaborate, celebrate wins, and create an environment where everyone can do their best work.
• Possibilities: Our belief shapes what’s next. Our technology powers the most reliable and energy-efficient connections around the world - and our team powers new products and markets that come next.

Responsibilities

• Design, implement, and debug complex logic blocks and integrate IPs from internal and external vendors.
• Support front-end integration tasks: Lint, CDC, synthesis, DFT, and ECO.
• Participate in design and code reviews to ensure quality.
• Develop testbenches and run RTL and gate-level simulations.
• Partner with verification, DFT, physical design, software, firmware, and systems teams on tape-outs and chip bring-up, validation, and debug.

Qualifications

Basic Qualifications

• BS/MS in Electrical Engineering or relevant field with ten or more years of ASIC design experience and a proven record of production tape-outs.
• Strong digital logic design skills, including complex synchronous/asynchronous interfaces, and proficiency in Verilog/SystemVerilog RTL.
• Experience with high-speed Serdes design and familiarity with Ethernet (802.3) standards.
• Knowledge of synthesis and static timing analysis.
• Experience with testbench/test case development (UVM familiarity), gate-level simulation, chip bring-up, and validation.

Preferred Qualifications

• Scripting expertise in Python, Tcl, Perl, and/or Shell.
• Familiarity with DFT methodology and the physical design flow.
• Knowledge of PCIe, UALink, or AXI/CHI interfaces.
• Hands-on STA and timing closure experience.

About Credo

Credo’s mission is to transform connectivity at scale through fast, reliable, and energy-efficient system solutions. Our high-speed copper and optical interconnect products deliver industry-leading power and performance at up to 1.6T to meet the ever-expanding data infrastructure demands of AI.

Our product portfolio includes ZeroFlap (ZF) Active Electrical Cables (AECs) and ZF optical transceivers, OmniConnect memory solutions, and a suite of retimers and DSPs for optical and copper Ethernet and PCIe, all leveraging the PILOT diagnostic and analytics software platform. Credo innovations enable our customers to connect the systems that connect the world.

Credo is committed to creating an inclusive environment for all employees and welcome applicants from diverse backgrounds without regard to race, color, religion, gender, sex, gender identity, sexual orientation, pregnancy, marital status, national origin, ethnicity, genetic information, age, disability, veteran status, or any other legally protected basis. If you have a disability or special need that requires accommodation to navigate our website or complete the application process, email [email protected]