Advanced Packaging & Integration Lead
Confirmed on the employer's own hiring board on Nov 7, 2026. First seen by Alion on Sep 21, 2026. Equal1 scores C on the Alion truth index.
We are seeking an experienced Advanced Packaging & Integration Lead to join our team and develop packaging solutions for multi-chip silicon spin-qubit devices within a scalable quantum system.
In this role, you will work with a multidisciplinary team to drive the R&D of complex multi-chip modules utilising TSVs and micro-bumps, optimised for operation at millikelvin temperatures. You will have a significant influence on the physical architecture of next-generation quantum processors, shaping how advanced packaging subsystems integrate into the overall quantum computing solution.
Main Duties and Responsibilities
Drive the high-level strategy and architectural design of 3D integrated circuits and multi-chip quantum modules.
Develop advanced packaging solutions using TSVs, fine-pitch micro-bumps, and flip-chip bonding.
Ensure packaging architectures and interconnects can withstand thermal cycling down to the millikelvin regime without delamination or loss of reliability.
Contribute to early-stage architecture and co-design activities, ensuring the advanced packaging subsystem scales with the requirements of the overall quantum system.
Develop simulation approaches to evaluate packaging and process options at DC and RF frequencies, including signal integrity, power integrity, thermal performance, and mechanical stress.
Balance R&D execution with a strong focus on yield improvement, failure analysis, manufacturability, and long-term hardware reliability.
Own relevant technical activities with external suppliers, OSATs, and research partners.
Support the transfer of novel packaging designs into external manufacturing and advanced packaging lines.
Experience and Qualifications
Required
Master’s or PhD in Electrical Engineering, Materials Science, Physics, Microelectronics, or a related field.
7+ years’ experience in 3D integration and advanced packaging, including TSVs, fine-pitch micro-bumps, and flip-chip bonding.
Experience with 3D-IC layout, planning, and simulation platforms for multi-die co-design, TSV floorplanning, and vertical interconnect planning.
Experience with multi-physics analysis tools such as Ansys HFSS/Q3D or equivalent for signal/power integrity, RF analysis, and cryogenic structural/thermal stress.
Experience managing technical transfers and working closely with external semiconductor advanced packaging facilities, OSATs, or research partners.
Proven ability to guide technical strategy and work effectively across multidisciplinary engineering teams.
Desired
Experience with cryogenic electronics, semiconductor physics, or silicon spin qubits.
Knowledge of material behaviour at extreme temperatures, including superconductors and low-loss dielectrics.
Experience leading or mentoring engineers in a high-tech, fast-paced R&D environment.