ASIC Synthesis & PPA Engineer
Confirmed on the employer's own hiring board on Oct 5, 2026. First seen by Alion on Sep 5, 2026. Ericsson scores B on the Alion truth index.
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About this opportunity:
Do you enjoy solving the hardest problems at the intersection of RTL, timing, power, area and physical implementation? This is an opportunity to take ownership and constraint development for high-performance, low power SoC designs.
We are hiring an experienced ASIC Synthesis & PPA Engineer. Your primary focus will be physical-aware synthesis, floorplan-driven netlist optimization, STA & QoR closure - while also actively identifying opportunities in RTL & microarchitecture level to improve the design PPA. You will work closely with RTL design, Integration, architecture, place-and-route, and DFT teams throughout the full design cycle.
What you will do:
- Execute physical-aware and floorplan-driven synthesis flows to reduce post-layout timing and congestion risks.
- Identify and resolve synthesis bottlenecks: critical path restructuring, datapath optimization, and register retiming.
- Drive QoR closure by tracking key metrics across design iterations and process corners while providing expert feedback on RTL coding guidelines and synthesizability.
- Work on PPA optimization and structured design space exploration.
- Run block-level and full-chip STA for timing analysis across PVT corners, support MMMC timing closure, and analyze clock domain crossing (CDC) checks.
- Validate UPF/CPF power intent implementation, including isolation cells, level shifters, and retention registers, for correctness and power impact.
- Collaborate with RTL, physical design, and silicon teams on early floorplan exploration, area optimization, pin assignment, and PPA trade-off analysis.
- Apply approved AI-assisted tools for log analysis, QoR comparison, and root cause investigation, while independently validating all generated results with sound engineering judgement.
The skills you bring:
- 8+ years of experience in physical synthesis or logic design implementation.
- Expert-level experience with Synopsys/Cadence EDA tools.
- Strong SDC constraints authoring and management skills, including clock definitions, generated clocks, I/O delays, and timing exceptions such as false paths and multicycle paths.
- Experience in low power design strategies.
- Experience in analyzing PPA results and providing actionable microarchitecture & RTL-level recommendations to improve the same.
- Proficiency in TCL; Python scripting is a strong plus.
- Multiple tape-outs on 7nm or below
Why join Ericsson? At Ericsson, you´ll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world’s toughest problems. You´ll be challenged, but you won’t be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next.
What happens once you apply?Click Here to find all you need to know about what our typical hiring process looks like.Encouraging a diverse and inclusive organization is core to our values at Ericsson, that's why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more.
Primary country and city: Sweden (SE) || Stockholm
Req ID: 790595