Staff DV Engineer

We are seeking Digital Design Verification Engineers to verify our custom ASICs for satellite and wireless telephony. Knowing Verilog, SystemVerilog, and UVM is a must, VHDL is valuable. We prioritize AI assistance to accelerate work.

Requirements

• HDL & Verification Methodology

  · Strong proficiency in Verilog and SystemVerilog

  · Experience writing tests within an existing UVM verification environment

  · Solid understanding of UVM architecture and methodology

  Programming & Scripting

  · Ability to write C/C++ code for verification purposes

  · Some scripting experience in Perl or Python

  Verification Planning & Execution

  · Ability to contribute to and help write test plans

  · Experience writing and maintaining verification tests

  · Ability to debug RTL simulations independently

  Leadership

  · Experience leading design verification efforts at the block level

  · Experience driving code coverage closure on assigned blocks

What you bring to this role:

• 6+ years of design verification experience in the semiconductor industry

Additional Requirements

This is a fast-paced, high-impact environment - flexibility to occasionally work extended hours or weekends during critical periods is expected.