Chip Package Signal and Power Integrity Engineer

About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As a Signal Integrity/Power Integrity Engineer, you'll lead chip and package design, ensuring optimal SI/PI performance and system co-design from concept to production. Collaborating within a cross-functional team, including Chip Design, IP, System Design, software, and vendors, you'll drive signal and power design implementations on chip and advanced packages.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving team behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google.

Responsibilities

• Lead SI/PI analysis for High-Performance Computing (HPC) utilizing 2.5D/3D package technologies to define specifications and optimize chip floorplans, power trees, and netlists.
• Drive next-generation memory interface development and evaluate high-speed Interface IPs, balancing complex trade-offs across IO PHY, SI/PI, and physical design.
• Own post-silicon validation and qualification of high-speed interfaces to ensure successful New Product Introduction (NPI).
• Partner with chip/system design teams, suppliers, and vendors to establish SI/PI goals, define design boundaries, and manage DFM trade-offs.
• Provide crucial feedback on chip floorplans to maximize package/system routability and SI/PI, while developing methodologies to improve simulation accuracy and productivity.

Qualifications

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

• 7 years of experience with SI/PI design for chip/package or system PCB.

• Experience in industry Signal integrity and Power Integrity (SIPI) modeling tool chains (e.g., HFSS, ADS, Sigrity, Siwave, etc.).

Preferred qualifications:

• Master’s degree or PhD in Electrical Engineering or SI/PI.
• Experience in 2.5D/3D package design, including silicon interposer, silicon bridge, and 3D die stacking technologies, and expertise in SI/PI analysis for high-speed interconnects.
• Knowledge of next-generation memory and chiplet standards, including timing budget, design and sign-off methodologies.
• Understanding of Static Timing Analysis, on-chip DVD/EMIR, system voltage budgets, and voltage regulator modeling and design.
• Proficient in Python, Matlab, or C++ to establish automation flows and advanced data processing/analysis.
• Ability to lead cross-functionally across chip design, physical design, STA, packaging, system, and validation teams.