Design Verification Manager, Silicon

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

• Lead and manage comprehensive verification activities for complex System-on-Chip (SoC) architectures, ensuring robust quality standards from pre-silicon to tape-out.
• Manage and mentor high-performing engineering teams, driving execution, fostering a culture of technical excellence, and supporting career growth.
• Drive SoC-level pre-silicon emulation strategies (e.g., Palladium, Zebu, SimXL) to accelerate hardware-software co-verification, boot operating systems, and catch complex system-level bugs early.
• Oversee complex post-silicon debug activities, collaborating closely with post-silicon validation teams to root-cause silicon issues, bring up hardware, and correlate pre-silicon verification coverage with actual silicon behavior.
• Develop and scale aspects of logic verification infrastructure and advanced methodologies across the SoC, maintaining strong integration standards with architecture, design, and cross-functional teams.

Qualifications

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
• 15 years of experience in front-end design or design verification.
• Experience in power-aware verification methodologies.
• Experience in fabric and interconnect architectures and cache coherency protocols.

Preferred qualifications:

• Master's degree in Electrical Engineering or Computer Science or equivalent practical experience.
• Experience in verification of high-bandwidth memory subsystems (DDR5, LPDDR5, HBM) including physical layer (PHY) training, memory controllers, and JEDEC compliance.
• Experience directly managing high-performing engineering teams with a proven track record of successfully delivering complex, production-grade SoCs.
• Experience in SoC-level verification and strong design verification (DV) fundamentals using universal verification methodology (UVM)-based environments, and with with pre-silicon emulation platforms and hardware accelerators (e.g., SimXL, formal verification, or portable stimulus standard/PSS).
• Excellent programming skills in SystemVerilog, Verilog, and scripting languages like Python or Perl.