Principal Engineer_RTL Design
Confirmed on the employer's own hiring board on Oct 18, 2026. First seen by Alion on Aug 20, 2026. Upscale AI scores A on the Alion truth index.
This is a full-time, on-site Principal ASIC Designer role based in the Greater Bengaluru Area. The individual will be responsible for end-to-end ASIC design activities, including architecture exploration, micro-architecture definition, logic design and RTL development.
Qualifications:
- Solid background in Digital IC Design, including micro-architecture, RTL design, logic synthesis, timing closure, and low-power design techniques.
- Familiarity with industry-standard EDA tools (e.g., Cadence, Synopsys, Mentor) for simulation, synthesis, and static timing analysis.
- Knowledge of ASIC design flows, verification methodologies, and an ability to collaborate with physical design and validation teams.
- Bachelor’s or Master’s degree in Electrical Engineering, Electronics, or a related field (or equivalent practical experience).
- Strong problem-solving skills, attention to detail, and an ability to work collaboratively in a cross-functional, on-site team environment.
- Passionate about ASIC innovation and getting defect-free ASICs to production while meeting time-to-market challenges
- Track record of success with multiple ASIC tape-outs
- 10+ years of industry experience in ASIC design.
- Experience with networking ASIC design is a plus.
- Experience in post-silicon ASIC bring-up is a plus.