Principal Engineer – Design Verification
Confirmed on the employer's own hiring board on Oct 1, 2026. First seen by Alion on Jul 14, 2026. Upscale AI scores B on the Alion truth index.
We are looking for a highly technical, hands-on Principal DV Engineer to anchor the verification of our next-generation, high-performance networking silicon. In this role, you will be the primary technical driver for complex IPs and critical sub-systems. You will balance advanced architectural environment creation with rigorous execution, leading by example on the engineering floor. This position is ideal for a veteran engineer who loves breaking complex designs, building elite UVM environments, and mentoring the next generation of verification talent.
Key Responsibilities
IP & Sub-system Leadership: Own the complete verification lifecycle for critical high-performance networking IPs and large-scale sub-systems.
UVM Environment Architecture: Architect, develop, and maintain advanced, scalable constrained-random verification environments from scratch using System Verilog and UVM.
Test Planning & Execution: Author comprehensive, bulletproof verification plans. Drive test case development, regressions, triage, and coverage closure (functional, code, and assertion-based metrics).
Advanced Debugging: Serve as the team's go-to expert for isolating and resolving the most complex, deep-seated hardware bugs.
Lead by Example: Actively participate in design and verification code reviews. Maintain high standards of code quality, reuse, and documentation within the execution team.
Cross-Functional Alignment: Partner closely with Design and Architecture teams to resolve ambiguities early in the design cycle and ensure high-quality delivery.
Required Qualifications & Skills
Experience: 15+ years of solid experience in ASIC/SoC Design Verification with a proven track record of successful tape-outs.
Domain Expertise: Extensive experience in the networking domain, verifying high-throughput, data-intensive designs.
Methodology Expert: Mastery of System Verilog and UVM. Must have a proven history of writing complex testbenches and VIP integrations from scratch.
Verification Scope: Proven experience leading verification at the IP and Sub-system level, with strong exposure to SoC integration.
Education: B Tech/M Tech in Electronics/Electrical Engineering, Computer Engineering, or a related field.
Preferred / Added Advantages
Hands-on experience with Formal Property Verification (FPV) to exhaustively verify block-level control logic.
Proficiency in Python or Perl for testbench automation and triage scripting.